aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Expand)AuthorFilesLines
2015-08-05gcc * config/rl78/rl78.c (rl78_force_nonfar_3): Remove optimizationNick Clifton1-7/+0
2015-08-05Disable AVX-512VL insns for scalar mode operands on -march=knl.Kirill Yukhin2-14/+23
2015-08-05Merge SSE and AVX ptest patterns.Kirill Yukhin2-25/+28
2015-08-04[MOXIE] Hookize PRINT_OPERAND and PRINT_OPERAND_ADDRESSAnatoly Sokolov3-10/+7
2015-08-04[AArch64] PR target/66731 Fix fnmul insn with -frounding-math (rtx costs)Szabolcs Nagy1-5/+17
2015-08-04aarch64.c: Change inner loop statement cost to be consistent with other targets.Pawel Kupidura1-8/+2
2015-08-04neon.md (neon_vget_lanev2di): Handle big-endian targets.Christophe Lyon1-1/+16
2015-08-04nvptx.h (struct nvptx_pseudo_info): Delete.Nathan Sidwell1-7/+0
2015-08-04[AArch64][14/14] Reuse target_option_current_node when passing pragma string ...Kyrylo Tkachov1-0/+12
2015-08-04[AArch64][11/14] Re-layout SIMD builtin types on builtin expansionKyrylo Tkachov4-3/+63
2015-08-04[AArch64][10/14] Implement target pragmasKyrylo Tkachov7-90/+237
2015-08-04[AArch64][9/14] Implement TARGET_CAN_INLINE_PKyrylo Tkachov1-0/+110
2015-08-04[AArch64][8/14] Implement TARGET_OPTION_VALID_ATTRIBUTE_PKyrylo Tkachov2-0/+502
2015-08-04[AArch64][7/14] Implement TARGET_SET_CURRENT_FUNCTIONKyrylo Tkachov2-0/+59
2015-08-04[AArch64][6/14] Implement TARGET_OPTION_SAVE/TARGET_OPTION_RESTOREKyrylo Tkachov4-59/+205
2015-08-04[AArch64][5/14] Make flag_omit_leaf_frame_pointer intialize to 2. Define and ...Kyrylo Tkachov1-1/+1
2015-08-04[AArch64][4/14] Create TARGET_FIX_ERR_A53_835769 and use that instead of aarc...Kyrylo Tkachov4-12/+17
2015-08-04i386.c (ix86_expand_int_movcc): Check result of ix86_expand_int_movcc as bool...Uros Bizjak1-1/+1
2015-08-04[AArch64][3/14] Refactor option override codeKyrylo Tkachov2-145/+308
2015-08-04[AArch64][2/14] Refactor arches handling, add arch enum identifierKyrylo Tkachov6-37/+56
2015-08-04[AArch64][1/14] Add ident field to struct processorKyrylo Tkachov1-8/+10
2015-08-03htm.md (tabort.): Restrict the source operand to using a base register.Peter Bergner1-1/+1
2015-08-03re PR target/67060 (FAIL: gcc.dg/pr56228.c (test for excess errors))John David Anglin1-6/+0
2015-08-03vector.md (VEC_L): Add KFmode and TFmode.Michael Meissner7-16/+209
2015-08-03[ARM] PR target/66731 Fix vnmul insn with -frounding-mathSzabolcs Nagy2-1/+31
2015-08-02arm.md (*arm_smin_cmp): New pattern.Michael Collison1-0/+38
2015-07-31re PR target/67049 (sh64-elf: internal compiler error: in df_uses_record, at ...Kaz Kojima1-1/+1
2015-07-31[ARM][2/3] Make if_neg_move and if_move_neg into insn_and_splitKyrylo Tkachov1-22/+38
2015-07-31m32r.c (m32r_attribute_identifier): New function.Nick Clifton1-0/+10
2015-07-31re PR go/66870 (split stack issues on ppc64le and ppc64)Alan Modra1-0/+4
2015-07-31Refactoring masked built-in decls to use proper mask type.Petr Murzin2-2134/+1919
2015-07-31[V850] Hookize LIBCALL_VALUEAnatoly Sokolov3-8/+14
2015-07-30[AArch64] Removed unused VRL2/3/4 iterator valuesAlan Lawrence1-12/+3
2015-07-30aarch64-simd.md (aarch64_ext<mode>): Replace call to GET_MODE_SIZE (GET_MODE_...David Sherwood7-25/+22
2015-07-30re PR target/66217 (PowerPC rotate/shift/mask instructions not optimal)Segher Boessenkool1-16/+19
2015-07-29Define DBX_REGISTER_NUMBER for IA MCUH.J. Lu1-0/+11
2015-07-29[AArch64] Add basic FP16 supportAlan Lawrence6-4/+119
2015-07-28arm.c (neon_element_bits, [...]): Call GET_MODE_INNER unconditionally.David Sherwood3-18/+10
2015-07-28fr30.md (indirect_jump): Use pmode_register_operand instead of nonimmediate_o...Richard Sandiford1-2/+2
2015-07-28[AArch64] Properly handle simple arith+extend ops in rtx costsKyrylo Tkachov1-2/+9
2015-07-28rl78.c (rl78_addsi3_internal): New function.Nick Clifton3-4/+32
2015-07-27[PATCH][AArch64] Improve spill code - swap order in shr patternsWilco Dijkstra1-13/+14
2015-07-27[ARM] PR/63870 Add a __builtin_lane_checkAlan Lawrence1-4/+34
2015-07-27[ARM] PR/63870 Add qualifier to check lane bounds in expandAlan Lawrence5-91/+101
2015-07-27[PATCH][AArch64] Improve spill code - swap order in shl patternWilco Dijkstra1-7/+7
2015-07-27arm-arches.def: Add "armv6kz".Matthew Wahab8-19/+39
2015-07-26alpha.c: Use SUBREG_P predicate.Uros Bizjak2-8/+8
2015-07-25re PR target/66930 (gengtype.c is miscompiled during stage2)Oleg Endo1-0/+1
2015-07-25i386.c: Use SUBREG_P predicate.Uros Bizjak4-33/+33
2015-07-25re PR target/67004 (valgrind error in recog_memoized & shorten_branches)Uros Bizjak1-5/+6
generated by cgit v1.1 at 2025-02-14 16:50:30 +0000