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2023-07-15hppa: Modify TLS patterns to provide both 32 and 64-bit support.John David Anglin1-34/+162
2023-07-14arm: [MVE intrinsics] rework vcmlaqChristophe Lyon5-310/+22
2023-07-14arm: [MVE intrinsics] factorize vcmlaqChristophe Lyon3-64/+29
2023-07-14arm: [MVE intrinsics] rework vcmulqChristophe Lyon4-448/+12
2023-07-14arm: [MVE intrinsics factorize vcmulqChristophe Lyon3-94/+33
2023-07-14arm: [MVE intrinsics] rework vcaddq vhcaddqChristophe Lyon5-1202/+117
2023-07-14arm: [MVE intrinsics] Factorize vcaddq vhcaddqChristophe Lyon3-117/+62
2023-07-14PR target/110588: Add *bt<mode>_setncqi_2 to generate btl on x86.Roger Sayle1-6/+23
2023-07-14i386: Improved insv of DImode/DFmode {high,low}parts into TImode.Roger Sayle1-10/+27
2023-07-14RISC-V: Enable COND_LEN_FMA auto-vectorizationJuzhe-Zhong3-0/+74
2023-07-14bpf: enable instruction schedulingJose E. Marchesi1-0/+11
2023-07-14RISC-V: Recognized zihintntl extensionsMonk Chiang1-0/+2
2023-07-14RISC-V: Remove the redundant expressions in the and<mode>3.Die Li1-5/+0
2023-07-14SH: Fix PR101496 peephole bugOleg Endo1-0/+39
2023-07-13pdp11: Fix epilogue generation [PR107841]Mikael Pettersson1-1/+1
2023-07-13Darwin: Use -platform_version when available [PR110624].Iain Sandoe1-3/+12
2023-07-13rs6000, Add return value to __builtin_set_fpscr_rnCarl Love3-21/+42
2023-07-13alpha: Fix computation mode in alpha_emit_set_long_cost [PR106966]Uros Bizjak1-1/+6
2023-07-13RISC-V: Refactor riscv mode after for VXRM and FRMPan Li1-23/+62
2023-07-13RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorizationJu-Zhe Zhong7-62/+675
2023-07-13RISC-V: Support COND_LEN_* patternsJuzhe-Zhong4-0/+169
2023-07-12i386: Fix FAIL of gcc.target/i386/pr91681-1.cRoger Sayle1-1/+1
2023-07-12i386: Fix FAIL of gcc.target/i386/pr91681-1.cRoger Sayle1-0/+33
2023-07-12PR target/110598: Fix rega = 0; rega ^= rega regression in i386.mdRoger Sayle1-2/+14
2023-07-12i386: Tweak ix86_expand_int_compare to use PTEST for vector equality.Roger Sayle1-1/+18
2023-07-12RISC-V: Support integer mult highpart auto-vectorizationJu-Zhe Zhong1-0/+30
2023-07-12x86: improve fast bfloat->float conversionJan Beulich1-8/+14
2023-07-12x86: make better use of VBROADCASTSS / VPBROADCASTDJan Beulich1-19/+42
2023-07-12riscv: thead: Factor out XThead*-specific peepholesChristoph Müllner3-56/+76
2023-07-12riscv: Prepare backend for index registersChristoph Müllner3-2/+26
2023-07-12riscv: Move address classification info types to riscv-protos.hChristoph Müllner2-43/+43
2023-07-12riscv: Define Xmode macroChristoph Müllner1-0/+4
2023-07-12riscv: Simplify output of MEM addressesChristoph Müllner1-1/+1
2023-07-12riscv: thead: Adjust constraints of th_addsl INSNChristoph Müllner1-3/+2
2023-07-12riscv: xtheadmempair: Fix doc for th_mempair_order_operands()Christoph Müllner1-2/+2
2023-07-12riscv: xtheadmempair: Fix CFA reg notesChristoph Müllner1-2/+6
2023-07-12riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extuChristoph Müllner2-3/+34
2023-07-12Break false dependence for vpternlog by inserting vpxor or setting constraint...liuhongt2-16/+137
2023-07-12Initial Granite Rapids D SupportMo, Zewei2-1/+6
2023-07-12i386: Guard 128 bit VAES builtins with AVX512VLHaochen Jiang2-5/+11
2023-07-12RISC-V: Optimize permutation codegen with vcompressJu-Zhe Zhong2-0/+157
2023-07-10rs6000: Remove redundant MEM_P predicate usagePeter Bergner1-2/+2
2023-07-10GCSE: Export 'insert_insn_end_basic_block' as global functionJu-Zhe Zhong1-124/+4
2023-07-10arm: Fix MVE intrinsics support with LTO (PR target/110268)Christophe Lyon3-30/+43
2023-07-10i386: Add new insvti_lowpart_1 and insvdi_lowpart_1 patterns.Roger Sayle1-0/+66
2023-07-10i386: Add AVX512 support for STV of SI/DImode rotation by constant.Roger Sayle1-1/+7
2023-07-10Add pre_reload splitter to detect fp min/max pattern.liuhongt1-0/+43
2023-07-07i386: Improve __int128 argument passing (in ix86_expand_move).Roger Sayle1-0/+28
2023-07-07IBM Z: Fix vec_init default expanderJuergen Christ1-5/+6
2023-07-07x86: slightly correct / simplify *vec_extractv2tiJan Beulich1-1/+1