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2024-05-13RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalarPan Li1-0/+51
2024-05-13[to-be-committed,RISC-V] Improve single inverted bit extraction - v3Jeff Law3-0/+43
2024-05-13Revert "MIPS: Support constraint 'w' for MSA instruction"YunQiang Su1-3/+0
2024-05-12arm: Use utxb rN, rM, ror #8 to implement zero_extract on armv6.Roger Sayle1-0/+66
2024-05-12[to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesisJeff Law1-4/+5
2024-05-12[to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usageJeff Law1-3/+3
2024-05-12Regenerate cygming.opt.urls and mingw.opt.urlsMark Wielaard2-5/+4
2024-05-11[PATCH v2 1/4] Support for CodeView debugging formatMark Harmstone1-0/+2
2024-05-10[RISC-V] Use shNadd for constant synthesisJeff Law1-0/+42
2024-05-10i386: Improve V[48]QI shifts on AVX512/SSE4.1Roger Sayle1-0/+3
2024-05-10pru: Fix register class checks in predicatesDimitar Dimitrov1-2/+2
2024-05-10bpf: fix printing of memory operands in pseudoc asm dialectJose E. Marchesi3-24/+21
2024-05-10c++, mingw: Fix up types of dtor hooks to __cxa_{,thread_}atexit/__cxa_throw ...Jakub Jelinek1-0/+16
2024-05-10RISC-V: Fix typos in code or comment [NFC]Kito Cheng2-50/+50
2024-05-09[committed] [RISC-V] Provide splitting guidance to combine to faciliate shNad...Jeff Law1-0/+17
2024-05-09MIPS: Support constraint 'w' for MSA instructionYunQiang Su1-0/+3
2024-05-09i386: Fix some intrinsics without alignment requirements.Hu, Lin12-9/+11
2024-05-09i386: fix ix86_hardreg_mov_ok with lra_in_progresskonglin11-1/+2
2024-05-08[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16Xiao Zeng2-25/+39
2024-05-08[RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synt...Jeff Law1-40/+41
2024-05-08RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4Christoph Müllner2-8/+21
2024-05-08RISC-V: Add zero_extract support for rv64gcChristoph Müllner1-0/+30
2024-05-08RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2Christoph Müllner2-4/+11
2024-05-08aarch64: Fix typo in aarch64-ldp-fusion.cc:combine_reg_notes [PR114936]Alex Coplan1-2/+2
2024-05-08AVR: target/114975 - Add combine-pattern for __parityqi2.Georg-Johann Lay1-1/+16
2024-05-08AVR: target/114975 - Add combine-pattern for __popcountqi2.Georg-Johann Lay1-0/+13
2024-05-08x86: Fix cmov cost model issue [PR109549]konglin11-1/+1
2024-05-07[committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuningJeff Law1-1/+1
2024-05-07[committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_PChristoph Müllner1-0/+18
2024-05-07[RISC-V] [PATCH v2] Enable inlining str* by defaultJeff Law2-4/+11
2024-05-07Rename "x86 Windows Options" to "Cygwin and MinGW Options"Zac Walker4-12/+12
2024-05-07aarch64: Add SEH to machine_functionZac Walker1-0/+6
2024-05-07aarch64: Add Cygwin and MinGW environments for AArch64Zac Walker2-0/+177
2024-05-07Exclude i386 functionality from aarch64 buildZac Walker3-3/+18
2024-05-07Rename section and encoding functions from i386 which will be used in aarch64Zac Walker3-26/+26
2024-05-07Reuse MinGW from i386 for AArch64Zac Walker13-10/+13
2024-05-07aarch64: Add aarch64-w64-mingw32 COFFZac Walker1-0/+91
2024-05-07aarch64: Mark x18 register as a fixed register for MS ABIZac Walker2-2/+39
2024-05-07aarch64: Preserve mem info on change of base for ldp/stp [PR114674]Alex Coplan1-4/+4
2024-05-07Remove obsolete Solaris 11.3 supportRainer Orth2-22/+10
2024-05-07Extend usdot_prodv*qi with vpmaddwd when AVXVNNI/AVX512VNNI is not available.liuhongt1-14/+41
2024-05-07Support dot_prod optabs for 64-bit vector.liuhongt1-0/+195
2024-05-07Optimize 64-bit vector permutation with punpcklqdq + 128-bit vector pshuf.liuhongt1-0/+71
2024-05-07pru: New validation pass for minrtDimitar Dimitrov3-0/+76
2024-05-07pru: Refactor to use passes definition fileDimitar Dimitrov5-27/+36
2024-05-07pru: Use HOST_WIDE_INT_1U macroDimitar Dimitrov1-2/+4
2024-05-07pru: Drop usage of ATTRIBUTE_UNUSEDDimitar Dimitrov3-17/+11
2024-05-07pru: Skip register save if function will not returnDimitar Dimitrov1-0/+4
2024-05-07pru: Add pattern variants for zero extending destinationDimitar Dimitrov1-6/+32
2024-05-07pru: Optimize the extzv and insv patternsDimitar Dimitrov1-9/+95
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