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2018-06-02[NDS32] Support Linux target for nds32.Chung-Ju Wu11-61/+317
2018-06-02[NDS32] Implement fp-as-gp optimization.Chung-Ju Wu6-54/+340
2018-06-01rs6000: Fix mangling for 128-bit floatSegher Boessenkool1-24/+7
2018-06-01[AArch64] Used prefer aliases SXTL(2) and UXTL(2)Kyrylo Tkachov1-2/+2
2018-06-01Fix SVE fallout from r260951Richard Sandiford1-4/+4
2018-06-012018-05-15 Michael Collison <michael.collison@arm.com>Michael Collison1-0/+10
2018-05-31sse.md (avx_vec_concat<mode>): Substitute concat_tg_mode mode attribute with ...Uros Bizjak1-11/+6
2018-05-31x86: Re-enable partial_reg_dependency and movx for HaswellH.J. Lu1-2/+2
2018-05-31Patch implementing vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics for AARCH64 ...Sameera Deshpande3-0/+1141
2018-05-30msp430.c (msp430_output_labelref): Prepend user_label_prefix to name.Jozef Lawrynowicz1-0/+3
2018-05-30msp430.md: Remove erroneous subreg expression from zero_extendqisi2 insn patt...Jozef Lawrynowicz1-3/+3
2018-05-31patch to add support of ARMv8.4 in saphiraSameera Deshpande1-2/+2
2018-05-30Reverting r260635Andre Vieira1-1/+1
2018-05-30[AArch64] Improve LDP/STP generation that requires a base registerJackson Woodruff1-97/+164
2018-05-30[AArch64] Fix aarch64_ira_change_pseudo_allocno_classWilco Dijkstra2-13/+16
2018-05-29RISC-V: Fix a comment typo.Jim Wilson1-1/+1
2018-05-29re PR target/85950 (Unsafe-math-optimizations regresses optimization using SS...Uros Bizjak1-5/+12
2018-05-29re PR target/85918 (Conversions to/from [unsigned] long long are not vectoriz...Jakub Jelinek2-2/+81
2018-05-28config.gcc: Identify FreeBSD 3.x and 4.x as unsupported.Gerald Pfeifer1-21/+7
2018-05-27pa-linux.h (NEED_INDICATE_EXEC_STACK): Define to 0.John David Anglin1-1/+4
2018-05-27Fix a number of ICE in the test suite.Paul Koning1-11/+0
2018-05-27[NDS32] Optimize movmem and setmem operations.Monk Chiang3-34/+186
2018-05-27[NDS32] Implement bswapsi2 and bswaphi2 patterns.Chung-Ju Wu1-0/+20
2018-05-27[NDS32] new attribute no_prologue and new option -mret-in-naked-func.Chung-Ju Wu3-8/+66
2018-05-27re PR target/85918 (Conversions to/from [unsigned] long long are not vectoriz...Jakub Jelinek3-25/+27
2018-05-25RISC-V: Add interrupt attribute support.Jim Wilson4-18/+125
2018-05-25re PR rtl-optimization/83628 (performance regression when accessing arrays on...Uros Bizjak3-70/+23
2018-05-25re PR target/85832 ([AVX512] possible shorter code when comparing with vector...Jakub Jelinek1-9/+13
2018-05-25Add IFN_COND_{MUL,DIV,MOD,RDIV}Richard Sandiford2-2/+54
2018-05-25[AArch64] Add SVE support for integer divisionRichard Sandiford2-0/+36
2018-05-25Fold VEC_COND_EXPRs to IFN_COND_* where possibleRichard Sandiford4-5/+101
2018-05-25Support SHF_EXCLUDE on non-x86 and with Solaris asRainer Orth2-0/+13
2018-05-25Add an "else" argument to IFN_COND_* functionsRichard Sandiford2-41/+52
2018-05-24sse.md (cvtusi2<ssescalarmodesuffix>64<round_name>): Add {q} suffix to insn m...Uros Bizjak1-1/+1
2018-05-24msp430.c (TARGET_WARN_FUNC_RETURN): Define.Jozef Lawrynowicz1-0/+11
2018-05-24re PR target/85903 (FAIL: gcc.target/i386/avx512dq-vcvtuqq2pd-2.c)Uros Bizjak1-5/+2
2018-05-24[AArch64, Falkor] Falkor address costs tuningLuis Machado1-1/+17
2018-05-24PR target/83009: Relax strict address checking for store pair lanesAndre Vieira1-1/+1
2018-05-23[Patch 02/02] Introduce prefetch-dynamic-strides optionLuis Machado2-0/+14
2018-05-23[Patch 01/02] Introduce prefetch-minimum stride optionLuis Machado2-1/+15
2018-05-23[arm] Remove mode26 feature bitKyrylo Tkachov2-16/+2
2018-05-23i386.md (*floatuns<SWI48:mode><MODEF:mode>2_avx512): New insn pattern.Uros Bizjak1-28/+93
2018-05-23[AArch64] Simplify frame pointer logicWilco Dijkstra1-17/+29
2018-05-23[AArch64][PR target/84882] Add mno-strict-alignSudakshina Das2-8/+5
2018-05-22[AArch64] Recognize a missed usage of a sbfiz instructionLuis Machado1-0/+14
2018-05-22[AArch64, patch] Refactor of aarch64-ldpstpJackson Woodruff3-167/+90
2018-05-22[AArch64] Merge stores of D-register values with different modesJackson Woodruff6-133/+124
2018-05-21re PR target/85657 (Make __ibm128 a separate type, even if long double uses t...Michael Meissner3-26/+46
2018-05-21[AArch64] Implement usadv16qi and ssadv16qi standard namesKyrylo Tkachov3-0/+80
2018-05-21i386.md (*movsf_internal): AVX falsedep fix.Alexander Nesterovskiy1-11/+17
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