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AgeCommit message (Expand)AuthorFilesLines
2024-06-25Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_typeKewen Lin72-259/+338
2024-06-25vms: Replace use of LONG_DOUBLE_TYPE_SIZEKewen Lin1-2/+3
2024-06-24[PATCH v2 2/3] RISC-V: setmem for RISCV with V extensionSergei Lewis3-2/+97
2024-06-24Fix MinGW option -mcrtdll=Pali Rohár2-0/+4
2024-06-24Add a late-combine pass [PR106594]Richard Sandiford3-0/+23
2024-06-24rtl-ssa: Rework _ignoring interfacesRichard Sandiford1-2/+2
2024-06-24rs6000: Eliminate unnecessary byte swaps for duplicated constant vector storeHaochen Gui1-0/+25
2024-06-23[PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()Artemiy Volkov1-1/+2
2024-06-23[committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extra...Jeff Law1-0/+1
2024-06-23AVX-512: Pacify -Wshift-overflow=2. [PR115409]Collin Funk2-3/+3
2024-06-22[PATCH v2] RISC-V: Remove integer vector eqne patterndemin.han4-275/+15
2024-06-21[committed] Fix testsuite fallout on stormy16 after IOR->PLUS changeJeff Law1-0/+14
2024-06-21xstormy16: Fix xs_hi_nonmemory_operandRichard Sandiford1-1/+1
2024-06-21iq2000: Fix test and branch instructionsRichard Sandiford2-3/+3
2024-06-21sh: Make *minus_plus_one work after RARichard Sandiford1-3/+3
2024-06-21MIPS: Set condmove cost to SET(REG, REG)YunQiang Su2-4/+28
2024-06-20rs6000: Fix wrong RTL patterns for vector merge high/low word on LEKewen Lin3-40/+76
2024-06-20i386: Allow all register_operand SUBREGs in x86_ternlog_idx.Roger Sayle1-9/+8
2024-06-20[RISC-V] Minor cleanup/improvement to bset/binv patternsJeff Law2-37/+25
2024-06-20i386: Fix some ISA bit test in option_overrideHongyu Wang1-5/+9
2024-06-19[PATCH v2] RISC-V: Remove float vector eqne patterndemin.han2-92/+2
2024-06-19i386: Zhaoxin shijidadao enablementmayshao7-8/+141
2024-06-19xtensa: Eliminate double MEMW insertions for volatile memoryTakayuki 'January June' Suwa1-1/+11
2024-06-19arm: Add support for MVE Tail-Predicated Low Overhead LoopsAndre Vieira8-55/+1424
2024-06-19xtensa: constantsynth: Reforge to fix some non-fatal issuesTakayuki 'January June' Suwa3-30/+103
2024-06-18RISC-V: Move mode assertion out of conditional branch in emit_insnEdwin Lu1-6/+19
2024-06-18RISC-V: Fix vwsll combine on rv32 targetsEdwin Lu1-4/+2
2024-06-18aarch64: Add comment about thunderxt81/t83 being aliasesAndrew Pinski1-0/+1
2024-06-18aarch64: make thunderxt88p1 an alias of thunderxt88Andrew Pinski2-4/+3
2024-06-18[to-be-committed,RISC-V] Improve bset generation when bit position is limitedJeff Law1-0/+36
2024-06-18aarch64: Add some uses of force_highpart_subregRichard Sandiford1-13/+4
2024-06-18aarch64: Add some uses of force_lowpart_subregRichard Sandiford4-17/+12
2024-06-18aarch64: Use force_subreg in more placesRichard Sandiford4-12/+10
2024-06-18rs6000: Shrink rs6000_init_generated_builtins size [PR115324]Jakub Jelinek2-12/+29
2024-06-18i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avxHu, Lin17-78/+104
2024-06-17[to-be-committed,RISC-V] Handle zero_extract destination for single bit inser...Jeff Law1-0/+17
2024-06-17rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]Peter Bergner1-5/+4
2024-06-17[to-be-committed,RISC-V] Improve variable bit set for rv64Jeff Law1-0/+12
2024-06-17i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.Hu, Lin12-64/+399
2024-06-17x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevectorLevy Hsu3-2/+48
2024-06-17s390: Extend two element float vectorStefan Schulze Frielinghaus1-0/+28
2024-06-17s390: Extend two/four element integer vectorsStefan Schulze Frielinghaus2-5/+28
2024-06-16aarch64: Fix reg_is_wrapped_separately array size [PR100211]Andrew Pinski1-1/+1
2024-06-16[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64Jeff Law1-0/+15
2024-06-15[committed] Fix minor SH scan-asm failure after recent IOR->ADD changesJeff Law1-0/+19
2024-06-15riscv: Allocate enough space to strcpy() stringChristoph Müllner1-3/+3
2024-06-14RISC-V: Bugfix vec_extract v mode iterator restriction mismatchPan Li1-1/+3
2024-06-14Adjust ix86_rtx_costs for pternlog_operand_p.liuhongt1-1/+38
2024-06-14Remove one_if_conv for latest Intel processors.liuhongt1-2/+2
2024-06-14i386: More use of m{32,64}bcst addressing modes with ternlog.Roger Sayle1-0/+63
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