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Age
Commit message (
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Author
Files
Lines
2024-06-25
Replace {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE with new hook mode_for_floating_type
Kewen Lin
72
-259
/
+338
2024-06-25
vms: Replace use of LONG_DOUBLE_TYPE_SIZE
Kewen Lin
1
-2
/
+3
2024-06-24
[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension
Sergei Lewis
3
-2
/
+97
2024-06-24
Fix MinGW option -mcrtdll=
Pali Rohár
2
-0
/
+4
2024-06-24
Add a late-combine pass [PR106594]
Richard Sandiford
3
-0
/
+23
2024-06-24
rtl-ssa: Rework _ignoring interfaces
Richard Sandiford
1
-2
/
+2
2024-06-24
rs6000: Eliminate unnecessary byte swaps for duplicated constant vector store
Haochen Gui
1
-0
/
+25
2024-06-23
[PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()
Artemiy Volkov
1
-1
/
+2
2024-06-23
[committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extra...
Jeff Law
1
-0
/
+1
2024-06-23
AVX-512: Pacify -Wshift-overflow=2. [PR115409]
Collin Funk
2
-3
/
+3
2024-06-22
[PATCH v2] RISC-V: Remove integer vector eqne pattern
demin.han
4
-275
/
+15
2024-06-21
[committed] Fix testsuite fallout on stormy16 after IOR->PLUS change
Jeff Law
1
-0
/
+14
2024-06-21
xstormy16: Fix xs_hi_nonmemory_operand
Richard Sandiford
1
-1
/
+1
2024-06-21
iq2000: Fix test and branch instructions
Richard Sandiford
2
-3
/
+3
2024-06-21
sh: Make *minus_plus_one work after RA
Richard Sandiford
1
-3
/
+3
2024-06-21
MIPS: Set condmove cost to SET(REG, REG)
YunQiang Su
2
-4
/
+28
2024-06-20
rs6000: Fix wrong RTL patterns for vector merge high/low word on LE
Kewen Lin
3
-40
/
+76
2024-06-20
i386: Allow all register_operand SUBREGs in x86_ternlog_idx.
Roger Sayle
1
-9
/
+8
2024-06-20
[RISC-V] Minor cleanup/improvement to bset/binv patterns
Jeff Law
2
-37
/
+25
2024-06-20
i386: Fix some ISA bit test in option_override
Hongyu Wang
1
-5
/
+9
2024-06-19
[PATCH v2] RISC-V: Remove float vector eqne pattern
demin.han
2
-92
/
+2
2024-06-19
i386: Zhaoxin shijidadao enablement
mayshao
7
-8
/
+141
2024-06-19
xtensa: Eliminate double MEMW insertions for volatile memory
Takayuki 'January June' Suwa
1
-1
/
+11
2024-06-19
arm: Add support for MVE Tail-Predicated Low Overhead Loops
Andre Vieira
8
-55
/
+1424
2024-06-19
xtensa: constantsynth: Reforge to fix some non-fatal issues
Takayuki 'January June' Suwa
3
-30
/
+103
2024-06-18
RISC-V: Move mode assertion out of conditional branch in emit_insn
Edwin Lu
1
-6
/
+19
2024-06-18
RISC-V: Fix vwsll combine on rv32 targets
Edwin Lu
1
-4
/
+2
2024-06-18
aarch64: Add comment about thunderxt81/t83 being aliases
Andrew Pinski
1
-0
/
+1
2024-06-18
aarch64: make thunderxt88p1 an alias of thunderxt88
Andrew Pinski
2
-4
/
+3
2024-06-18
[to-be-committed,RISC-V] Improve bset generation when bit position is limited
Jeff Law
1
-0
/
+36
2024-06-18
aarch64: Add some uses of force_highpart_subreg
Richard Sandiford
1
-13
/
+4
2024-06-18
aarch64: Add some uses of force_lowpart_subreg
Richard Sandiford
4
-17
/
+12
2024-06-18
aarch64: Use force_subreg in more places
Richard Sandiford
4
-12
/
+10
2024-06-18
rs6000: Shrink rs6000_init_generated_builtins size [PR115324]
Jakub Jelinek
2
-12
/
+29
2024-06-18
i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx
Hu, Lin1
7
-78
/
+104
2024-06-17
[to-be-committed,RISC-V] Handle zero_extract destination for single bit inser...
Jeff Law
1
-0
/
+17
2024-06-17
rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]
Peter Bergner
1
-5
/
+4
2024-06-17
[to-be-committed,RISC-V] Improve variable bit set for rv64
Jeff Law
1
-0
/
+12
2024-06-17
i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.
Hu, Lin1
2
-64
/
+399
2024-06-17
x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevector
Levy Hsu
3
-2
/
+48
2024-06-17
s390: Extend two element float vector
Stefan Schulze Frielinghaus
1
-0
/
+28
2024-06-17
s390: Extend two/four element integer vectors
Stefan Schulze Frielinghaus
2
-5
/
+28
2024-06-16
aarch64: Fix reg_is_wrapped_separately array size [PR100211]
Andrew Pinski
1
-1
/
+1
2024-06-16
[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64
Jeff Law
1
-0
/
+15
2024-06-15
[committed] Fix minor SH scan-asm failure after recent IOR->ADD changes
Jeff Law
1
-0
/
+19
2024-06-15
riscv: Allocate enough space to strcpy() string
Christoph Müllner
1
-3
/
+3
2024-06-14
RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
Pan Li
1
-1
/
+3
2024-06-14
Adjust ix86_rtx_costs for pternlog_operand_p.
liuhongt
1
-1
/
+38
2024-06-14
Remove one_if_conv for latest Intel processors.
liuhongt
1
-2
/
+2
2024-06-14
i386: More use of m{32,64}bcst addressing modes with ternlog.
Roger Sayle
1
-0
/
+63
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