riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-24	i386: Update i386-builtin.def file comment description of BDESC{,_FIRST}	Jakub Jelinek	1	-2/+2
2023-02-24	aarch64: Update FLAGS field documentation comment in aarch64-cores.def	Kyrylo Tkachov	1	-1/+4
2023-02-24	i386: Fix up builtins used in avx512bf16vlintrin.h [PR108881]	Jakub Jelinek	1	-16/+16
2023-02-24	RTEMS: Tune multilib selection	Sebastian Huber	1	-8/+9
2023-02-24	MIPS: Add pattern for clo	Junxian Zhu	1	-0/+9
2023-02-24	Hazard barrier return support	Junxian Zhu	3	-0/+19
2023-02-23	gcc: xtensa: update include style in xtensa-dynconfig.cc	Max Filippov	1	-5/+5
2023-02-23	gcc: xtensa: rename xtensa-dynconfig.c and update its build rule	Max Filippov	2	-4/+3
2023-02-23	xtensa: Eliminate unnecessary general-purpose reg-reg moves	Takayuki 'January June' Suwa	1	-0/+46
2023-02-23	xtensa: Eliminate the use of callee-saved register that saves and restores on...	Takayuki 'January June' Suwa	1	-25/+107
2023-02-23	xtensa: Fix up fatal_error message strings in xtensa-dynconfig.c [PR108890]	Jakub Jelinek	1	-4/+4
2023-02-23	xtensa: Fix missing mode warnings in machine description	Takayuki 'January June' Suwa	1	-6/+6
2023-02-23	xtensa: fix PR target/108876	Max Filippov	1	-3/+3
2023-02-23	Revert "gcc: xtensa: fix PR target/108876"	Max Filippov	2	-13/+9
2023-02-22	RISC-V: Add RVV reduction C/C++ intrinsics support	Ju-Zhe Zhong	11	-14/+668
2023-02-22	RISC-V: Add floating-point RVV C/C++ api	Ju-Zhe Zhong	11	-211/+2998
2023-02-21	gcc: xtensa: fix PR target/108876	Max Filippov	2	-9/+13
2023-02-20	xtensa: Enforce return address saving when -Og is specified	Takayuki 'January June' Suwa	1	-2/+5
2023-02-20	i386: Introduce general_x64constmem_operand predicate	Uros Bizjak	2	-8/+15
2023-02-20	powerpc: Another umaddditi4 fix [PR108862]	Jakub Jelinek	1	-2/+2
2023-02-20	RISC-V: prefetch.* only take base register with zero-offset for the address	Kito Cheng	1	-2/+2
2023-02-18	i386: Fix up replacement of registers in certain peephole2s [PR108832]	Jakub Jelinek	3	-5/+44
2023-02-18	LoongArch: Fix multiarch tuple canonization	Xi Ruoyao	1	-1/+1
2023-02-17	ii386: Generate QImode binary ops with high-part input register [PR108831]	Uros Bizjak	2	-0/+71
2023-02-17	RISC-V: Add RVV all mask C/C++ intrinsics support	Ju-Zhe Zhong	9	-20/+511
2023-02-17	RISC-V: Rename tu_preds to none_tu_preds [NFC]	Ju-Zhe Zhong	2	-9/+9
2023-02-17	RISC-V: Normalize SEW = 64 handling into a simplified function	Ju-Zhe Zhong	3	-503/+316
2023-02-17	RISC-V: Rearrange the organization of declarations of RVV intrinsics [NFC]	Ju-Zhe Zhong	1	-101/+161
2023-02-17	RISC-V: Move saturating add/subtract md pattern location [NFC]	Ju-Zhe Zhong	1	-245/+245
2023-02-17	RISC-V: Remove "extern" for namespace [NFC]	Ju-Zhe Zhong	1	-20/+20
2023-02-17	RISC-V: Replace simm32_p with immediate_operand (Pmode)	Ju-Zhe Zhong	3	-28/+17
2023-02-15	Fix PR target/90458	Eric Botcazou	1	-3/+8
2023-02-15	Fix an accidental double space	Jan-Benedict Glaw	1	-1/+1
2023-02-15	i386: Relax extract location operand mode requirements	Uros Bizjak	1	-67/+67
2023-02-15	i386: Rename extr_register_operand to int248_register_operand	Uros Bizjak	2	-41/+14
2023-02-15	RISC-V: Finish all integer C/C++ intrinsics	Ju-Zhe Zhong	9	-20/+1079
2023-02-15	RISC-V: Add integer compare C/C++ intrinsic support	Ju-Zhe Zhong	12	-41/+999
2023-02-15	powerpc: Fix up expansion for WIDEN_MULT_PLUS_EXPR [PR108787]	Jakub Jelinek	1	-9/+24
2023-02-15	target/108738 - optimize bit operations in STV	Richard Biener	1	-10/+8
2023-02-15	target/108738 - STV bitmap operations compile-time hog	Richard Biener	1	-23/+26
2023-02-14	bpf: fix memory constraint of ldx/stx instructions [PR108790]	David Faust	2	-5/+16
2023-02-13	i386: Relax extract location operand mode requirements [PR108516]	Uros Bizjak	2	-2/+23
2023-02-13	IBM zSystems: Do not propagate scheduler state across basic blocks [PR108102]	Stefan Schulze Frielinghaus	1	-35/+7
2023-02-13	IBM zSystems: Fix predicate execute_operation	Stefan Schulze Frielinghaus	1	-2/+2
2023-02-13	RISC-V: Handle vlenb correctly in unwinding	Kito Cheng	1	-0/+7
2023-02-12	RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.	Jin Ma	1	-4/+6
2023-02-12	RISC-V: Add fixed-point support	Ju-Zhe Zhong	5	-13/+346
2023-02-12	RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support	Ju-Zhe Zhong	12	-56/+536
2023-02-12	RISC-V: Add vmadc/vmsbc C/C++ API support	Ju-Zhe Zhong	9	-1/+642
2023-02-12	RISC-V: Add vadc/vsbc C/C++ API support	Ju-Zhe Zhong	11	-7/+429