aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Expand)AuthorFilesLines
2018-05-25Add IFN_COND_{MUL,DIV,MOD,RDIV}Richard Sandiford2-2/+54
2018-05-25[AArch64] Add SVE support for integer divisionRichard Sandiford2-0/+36
2018-05-25Fold VEC_COND_EXPRs to IFN_COND_* where possibleRichard Sandiford4-5/+101
2018-05-25Support SHF_EXCLUDE on non-x86 and with Solaris asRainer Orth2-0/+13
2018-05-25Add an "else" argument to IFN_COND_* functionsRichard Sandiford2-41/+52
2018-05-24sse.md (cvtusi2<ssescalarmodesuffix>64<round_name>): Add {q} suffix to insn m...Uros Bizjak1-1/+1
2018-05-24msp430.c (TARGET_WARN_FUNC_RETURN): Define.Jozef Lawrynowicz1-0/+11
2018-05-24re PR target/85903 (FAIL: gcc.target/i386/avx512dq-vcvtuqq2pd-2.c)Uros Bizjak1-5/+2
2018-05-24[AArch64, Falkor] Falkor address costs tuningLuis Machado1-1/+17
2018-05-24PR target/83009: Relax strict address checking for store pair lanesAndre Vieira1-1/+1
2018-05-23[Patch 02/02] Introduce prefetch-dynamic-strides optionLuis Machado2-0/+14
2018-05-23[Patch 01/02] Introduce prefetch-minimum stride optionLuis Machado2-1/+15
2018-05-23[arm] Remove mode26 feature bitKyrylo Tkachov2-16/+2
2018-05-23i386.md (*floatuns<SWI48:mode><MODEF:mode>2_avx512): New insn pattern.Uros Bizjak1-28/+93
2018-05-23[AArch64] Simplify frame pointer logicWilco Dijkstra1-17/+29
2018-05-23[AArch64][PR target/84882] Add mno-strict-alignSudakshina Das2-8/+5
2018-05-22[AArch64] Recognize a missed usage of a sbfiz instructionLuis Machado1-0/+14
2018-05-22[AArch64, patch] Refactor of aarch64-ldpstpJackson Woodruff3-167/+90
2018-05-22[AArch64] Merge stores of D-register values with different modesJackson Woodruff6-133/+124
2018-05-21re PR target/85657 (Make __ibm128 a separate type, even if long double uses t...Michael Meissner3-26/+46
2018-05-21[AArch64] Implement usadv16qi and ssadv16qi standard namesKyrylo Tkachov3-0/+80
2018-05-21i386.md (*movsf_internal): AVX falsedep fix.Alexander Nesterovskiy1-11/+17
2018-05-21Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-aTamar Christina4-18/+124
2018-05-21[ARC] Add multilib support for linux targetsAlexey Brodkin1-0/+25
2018-05-20[NDS32] Set call address constraint.Chung-Ju Wu2-4/+9
2018-05-20[NDS32] Adjust register move cost for graywolf cpu.Kito Cheng1-2/+22
2018-05-20[NDS32] Rewrite cost model.Kito Cheng3-67/+543
2018-05-20[NDS32] Print pipeline model in asm header.Chung-Ju Wu2-0/+54
2018-05-19[NDS32] Update copyright year in nds32-fpu.md.Monk Chiang1-1/+1
2018-05-19[NDS32] Adjust ASM spec.Chung-Ju Wu1-1/+6
2018-05-19[NDS32] New option -minline-asm-r15.Chung-Ju Wu2-2/+9
2018-05-19[NDS32] Add abssi2 pattern.Chung-Ju Wu1-0/+14
2018-05-19i386.md (rex64namesuffix): New mode attribute.Uros Bizjak2-219/+67
2018-05-19[NDS32] Refine functions that deal with lwm and smw operations.Chung-Ju Wu2-23/+72
2018-05-19[NDS32] Refine nds32-md-auxiliary.c.Chung-Ju Wu1-18/+8
2018-05-19[NDS32] Support PIC and TLS.Kuan-Lin Chen11-137/+1036
2018-05-19[NDS32] Use machine mode with E_ prefix.Chung-Ju Wu1-2/+2
2018-05-19[NDS32] Implment indirect funciton call attribute.Kuan-Lin Chen10-25/+461
2018-05-18RISC-V: Add RV32E support.Kito Cheng5-8/+44
2018-05-18re PR bootstrap/85838 (-Wmaybe-uninitialized warning in sparc.c (sparc_expand...Eric Botcazou1-0/+2
2018-05-18[arm][2/2] Remove support for -march=armv3 and olderKyrylo Tkachov9-371/+85
2018-05-18[arm][1/2] Remove support for deprecated -march=armv5 and armv5eKyrylo Tkachov11-122/+85
2018-05-18[AArch64] Unify vec_set patterns, support floating-point vector modes properlyKyrylo Tkachov1-76/+9
2018-05-18Replace FMA_EXPR with one internal fn per optabRichard Sandiford2-15/+30
2018-05-17RISC-V: Optimize switch with sign-extended index.Jim Wilson1-2/+12
2018-05-17thunderx2t99.md (thunderx2t99_ls_both): Delete.Steve Ellcey1-50/+60
2018-05-17arm_cmse.h (cmse_nsfptr_create, [...]): Remove #include <stdint.h>.Jerome Lambourg1-3/+2
2018-05-17re PR tree-optimization/85698 (CPU2017 525.x264_r fails starting with r257581)Pat Haugen1-1/+1
2018-05-17re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)Jakub Jelinek1-11/+31
2018-05-17re PR target/85323 (SSE/AVX/AVX512 shift by 0 not optimized away)Jakub Jelinek1-8/+155
generated by cgit v1.1 at 2024-10-04 13:57:53 +0000