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2015-11-10constraints.md (wF constraint): New constraints for power9/toc fusion.Michael Meissner6-112/+1410
2015-11-09visium.h (PRINT_OPERAND): Delete.Eric Botcazou2-64/+29
2015-11-09i386.md (*strmovqi_1): Fix insn enable condition.Uros Bizjak1-2/+2
2015-11-09rs6000.opt (-mpower9-fusion): Add new switches for ISA 3.0 (power9).Michael Meissner10-20/+262
2015-11-09[AArch64][cleanup] Remove uses of CONST_DOUBLE_HIGH, CONST_DOUBLE_LOWKyrylo Tkachov1-24/+8
2015-11-09[AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INTKyrylo Tkachov3-6/+7
2015-11-09Machine modes for address printing.Julian Brown45-238/+235
2015-11-09Support init priority on SolarisRainer Orth3-13/+9
2015-11-09i386: Add address spaces for fs/gs segments and tlsRichard Henderson6-79/+195
2015-11-09i386: Disallow address spaces with string insnsRichard Henderson3-32/+89
2015-11-09i386: Handle address spaces in movabs patternsRichard Henderson1-6/+26
2015-11-08Merge of the scalar-storage-order branch.Eric Botcazou4-5/+5
2015-11-07* config/sparc/sparc.opt (mfix-at697f): Add final period.Eric Botcazou1-1/+1
2015-11-06revert: arm.md (*arm_smin_cmp): New pattern.Michael Collison1-38/+0
2015-11-06[AArch64] Fix vqtb[lx][234] on big-endianChristophe Lyon3-451/+459
2015-11-06[Patch AArch64] Switch constant pools to separate rodata sections.Ramana Radhakrishnan1-9/+23
2015-11-06[Patch ARM] Unified assembler in ARM state.Ramana Radhakrishnan8-274/+231
2015-11-06aarch64-builtins.c: Builtins for rsqrt and rsqrtf.Benedikt Huber7-2/+260
2015-11-06[ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulato...Kyrylo Tkachov1-0/+6
2015-11-06Update loongson vector reductions.Simon Dardis1-24/+32
2015-11-06tree-vectorizer.h (struct _bb_vec_info): Add region_begin/end members.Richard Biener2-0/+2
2015-11-05target.def (goacc.dim_limit): New hook.Nathan Sidwell1-0/+22
2015-11-04nvptx.c (nvptx_goacc_validate_dims): Add checking.Nathan Sidwell1-2/+23
2015-11-04nvptx.c: Include gimple headers.Nathan Sidwell1-5/+627
2015-11-04Pass manager: add support for termination of pass listMartin Liska2-0/+2
2015-11-03remove unused config/arm/coff.hTrevor Saunders1-82/+0
2015-11-03[AARCH64][PATCH 1/3] Implementing the variants of the vmulx_ NEON intrinsicBilyan Borisov4-68/+51
2015-11-03[AArch64] Fix ICE on (const_double:HF 0.0)Alan Lawrence1-1/+1
2015-11-02freebsd64.h (ASM_SPEC32): Adust spec to handle PIE executables.Andreas Tobler1-1/+1
2015-11-02[ARM] neon-testgen.ml typoJulian Brown1-7/+7
2015-11-01* config/mcore/mcore.c: Include regs.h.Jeff Law1-0/+1
2015-10-31rs6000: Rewrite rs6000_reg_live_or_pic_offset_pSegher Boessenkool1-15/+20
2015-10-31rs6000: Another PIC LRA fixSegher Boessenkool1-1/+3
2015-10-30nvptx.h (HARD_REGNO_NREGS): Avoid warning on unused args.Jeff Law1-2/+2
2015-10-30Makefile.in (OBJS): Add multiple_target.o.Evgeny Stupachenko1-18/+0
2015-10-30Fix comment typo.Jim Wilson1-1/+1
2015-10-30[ARM] Fix checking RTL error in cortex_a9_sched_adjust_costKyrylo Tkachov1-3/+1
2015-10-30libgcc changes for AMD znver1.Venkataramanan Kumar1-0/+6
2015-10-30[AArch64] Fix insn types.Evandro Menezes1-4/+4
2015-10-29[PATCH 8/9] ENABLE_CHECKING refactoring: target-specific partsMikhail Maltsev9-139/+126
2015-10-30sh.opt: Fix format of the help text for -mfdpicKaz Kojima1-1/+1
2015-10-30[MCORE] Hookize GO_IF_LEGITIMATE_ADDRESSAnatoly Sokolov2-85/+75
2015-10-29rs6000: Save the PIC reg when neededSegher Boessenkool1-22/+22
2015-10-29Fix target/68124Richard Henderson1-15/+21
2015-10-29rs6000.c (rs6000_init_libfuncs): Split libfunc setup into 3 functions...Michael Meissner2-277/+591
2015-10-29rs6000.h (ALTIVEC_VECTOR_MODE): Add IEEE 128-bit floating point modes that ca...Michael Meissner7-93/+108
2015-10-28nvptx.c (nvptx_print_operand): Remove 'd' case.Nathan Sidwell1-19/+4
2015-10-28re PR target/67839 (Bit addressable instructions generated for invalid memory...Senthil Kumar Selvaraj1-2/+2
2015-10-28Handle noplt in call expanders for AArch64.Ramana Radhakrishnan1-10/+14
2015-10-28nvptx.h (struct machine_function): Add axis_predicate.Nathan Sidwell4-23/+1320
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