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AgeCommit message (Expand)AuthorFilesLines
2019-02-05S/390: Remove load and test fp splitterAndreas Krebbel1-18/+3
2019-02-05re PR target/89112 (Incorrect code generated by rs6000 memcmp expansion)Aaron Sawdey1-25/+42
2019-02-05re PR target/89112 (Incorrect code generated by rs6000 memcmp expansion)Aaron Sawdey1-2/+2
2019-02-04[RS6000] Fix potiential buffer overflowAlan Modra1-2/+39
2019-02-04[RS6000] Emit inline PLT when -mno-tls-markersAlan Modra2-15/+8
2019-02-04sparc.h: Remove superfluous blank lines.Eric Botcazou2-80/+76
2019-02-04[NDS32] Change naming rule for dyanmic linker.Kito Cheng1-1/+19
2019-02-04[NDS32] Restrict address mode, when symbol is TLS model.Chung-Ju Wu1-1/+1
2019-02-04[NDS32] Remove all -mtlsdesc-trmpoline related things.Chung-Ju Wu1-9/+1
2019-02-03re PR target/89071 (AVX vcvtsd2ss lets us avoid PXOR dependency breaking for ...Uros Bizjak1-27/+57
2019-02-02re PR middle-end/87887 (ICE in make_ssa_name_fn, at tree-ssanames.c:269)Jakub Jelinek1-3/+8
2019-01-31re PR target/89071 (AVX vcvtsd2ss lets us avoid PXOR dependency breaking for ...Uros Bizjak1-17/+22
2019-01-30re PR target/87064 (libgomp.oacc-fortran/reduction-3.f90 fails starting with ...Bill Schmidt1-1/+1
2019-01-30rs6000-c.c (altivec-resolve_overloaded_builtin): Change handling of ALTIVEC_B...Kelvin Nilsen1-1/+7
2019-01-30re PR c++/89105 (-Wabi warns for functions with internal linkage)Jakub Jelinek1-0/+4
2019-01-27re PR target/87214 (r263772 miscompiled 520.omnetpp_r in SPEC CPU 2017)Jakub Jelinek1-59/+71
2019-01-25This is pretty unlikely in real code...Richard Earnshaw1-14/+58
2019-01-25[PATCH][AArch64] Fix generation of tst (PR87763)Wilco Dijkstra1-1/+1
2019-01-25[AArch64][SVE] Handle register-register pred_movsRichard Sandiford1-7/+11
2019-01-24altivec.md (build_vector_mask_for_load): Use MEM_P.Peter Bergner15-352/+335
2019-01-24re PR debug/89006 (New note: non-delegitimized UNSPEC UNSPEC_SET_GOT (14) fou...Jakub Jelinek1-0/+2
2019-01-23re PR target/88998 (bad codegen with mmx instructions for unordered_map)Uros Bizjak1-17/+29
2019-01-23aarch64: fix use-after-free in -march=native (PR driver/89014)David Malcolm1-6/+6
2019-01-23[ARC] atomics: Add operand to DMB instructionVineet Gupta1-1/+1
2019-01-22re PR target/88965 (powerpc64le vector builtin hits ICE in verify_gimple)Jakub Jelinek1-0/+30
2019-01-22re PR target/87064 (libgomp.oacc-fortran/reduction-3.f90 fails starting with ...Jakub Jelinek1-1/+1
2019-01-22[arm] Further fixes for PR88469Richard Earnshaw1-1/+1
2019-01-22i386: Add mask2 to builtin_descriptionHongtao Liu2-3225/+3110
2019-01-22i386: Load external function address via GOT slotH.J. Lu1-1/+5
2019-01-22[arm] PR target/88469 fix incorrect argument passing with 64-bit bitfieldsRichard Earnshaw1-4/+28
2019-01-22sparc.c (parc_delegitimize_address): Recognize the GOT register and decoded H...Eric Botcazou1-11/+17
2019-01-22[RS6000] PR88614, output_operand: invalid %z valueAlan Modra5-161/+174
2019-01-21re PR target/88938 (ICE in extract_insn, at recog.c:2304)Uros Bizjak1-0/+10
2019-01-21i386: Move Intel intrinsics head files to <immintrin.h>H.J. Lu14-55/+51
2019-01-19aarch64.c (aarch64_stack_protect_guard): Move outside of #if CHECKING_P code.Jakub Jelinek1-13/+13
2019-01-18rs6000: Fix *movsi_from_df (PR88892)Segher Boessenkool1-14/+9
2019-01-18PR target/88799 Add +mp and +sec extensions to ARMv7-aRichard Earnshaw3-5/+28
2019-01-18[AArch64] Add support for system register based stack protector canary accessRamana Radhakrishnan4-4/+147
2019-01-18re PR target/88734 (AArch64's ACLE intrinsics give an ICE instead of compile ...Jakub Jelinek1-2/+2
2019-01-18re PR target/88734 (AArch64's ACLE intrinsics give an ICE instead of compile ...Jakub Jelinek1-5/+5
2019-01-17aarch64.c (cgraph.h): New include.Steve Ellcey2-0/+162
2019-01-17GCN back-end codeAndrew Stubbs13-0/+8991
2019-01-17GCN machine descriptionAndrew Stubbs4-0/+5244
2019-01-17Rename stack-clash protection CFA register to avoid clashTamar Christina2-10/+26
2019-01-17[AArch64] Initial -mcpu=ares tuningKyrylo Tkachov2-1/+27
2019-01-17re PR target/88794 (fixupimm intrinsics are unusable)Wei Xiao7-336/+347
2019-01-17re PR target/88794 (fixupimm intrinsics are unusable)Wei Xiao1-6/+36
2019-01-17re PR target/88794 (fixupimm intrinsics are unusable)Wei Xiao1-2/+1
2019-01-17[rs6000] Support more prototypes for vec_ld and vec_st.Kewen Lin1-0/+20
2019-01-16aarch64-builtins.c (aarch64_simd_expand_args): Use correct max nunits for end...Tamar Christina2-12/+31
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