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AgeCommit message (Expand)AuthorFilesLines
2024-04-25rs6000: Use bcdsub. instead of bcdadd. for bcd invalid number checkingHaochen Gui1-3/+3
2024-04-24Revert "RISC-V: Support highpart register overlap for vwcvt"Pan Li4-68/+19
2024-04-24bpf: define BPF feature pre-processor macrosJose E. Marchesi3-17/+92
2024-04-24i386: Fix behavior for both using AVX10.1-256 in options and function attributeHaochen Jiang1-0/+1
2024-04-24Revert "RISC-V: Support highpart overlap for vext.vf"Pan Li1-10/+9
2024-04-23i386: Avoid =&r,r,r andn double-word alternative for ia32 [PR114810]Jakub Jelinek1-4/+5
2024-04-23Further spelling fixes in translatable stringsJakub Jelinek1-1/+1
2024-04-23Spelling fixes for translatable stringsJakub Jelinek2-2/+2
2024-04-23s390x: Fix vec_xl/vec_xst type aliasing [PR114676]Andreas Krebbel1-7/+9
2024-04-23LoongArch: Define builtin macros for ISA evolutionsYang Yujie10-94/+397
2024-04-23LoongArch: Define ISA versionsYang Yujie12-131/+246
2024-04-23RISC-V: Adjust overlap attr after revert d3544cea63d and e65aaf8efe1Pan Li1-1/+1
2024-04-22Revert "RISC-V: Rename vconstraint into group_overlap"Pan Li3-19/+16
2024-04-22Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute"Pan Li1-17/+2
2024-04-22s390x: Do not default to -mvx for -mesaAndreas Krebbel1-1/+1
2024-04-22Revert "RISC-V: Support highpart overlap for floating-point widen instructions"Pan Li1-41/+37
2024-04-22Revert "RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST...Pan Li1-33/+30
2024-04-22Revert "RISC-V: Support highest-number regno overlap for widen ternary"Pan Li1-60/+55
2024-04-22Revert "RISC-V: Support widening register overlap for vf4/vf8"Pan Li1-20/+18
2024-04-21Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions"Pan Li1-34/+31
2024-04-20Revert "RISC-V: Fix overlap group incorrect overlap on v0"Pan Li1-134/+134
2024-04-20Revert "RISC-V: Support highest overlap for wv instructions"Pan Li1-46/+42
2024-04-20Revert "RISC-V: Support one more overlap for wv instructions"Pan Li2-52/+46
2024-04-20i386: Fix up *avx2_eq<mode>3 constraints [PR114783]Jakub Jelinek1-1/+1
2024-04-19bpf: remove huge memory waste with string allocation.Cupertino Miranda1-19/+38
2024-04-19bpf: support more instructions to match CO-RE relocationsCupertino Miranda7-56/+156
2024-04-19[vxworks] avoid mangling __STDC_VERSION_LIMITS_H__Alexandre Oliva1-1/+1
2024-04-18AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114...Tamar Christina1-8/+15
2024-04-17AVR: target/114752 - Fix ICE on inline asm const 64-bit float operandGeorg-Johann Lay1-4/+13
2024-04-16optimize Zicond conditional select cases.Fei Gao1-1/+1
2024-04-16LoongArch: Add indexes for some compilation options.Lulu Cheng11-12/+17
2024-04-15AVR: Add 8 more avrxmega3 MCUs.Georg-Johann Lay1-0/+8
2024-04-15RISC-V: Add VLS to mask vec_extract [PR114668].Robin Dapp1-2/+2
2024-04-15x86: Allow TImode offsettable memory only with 8-bit constantH.J. Lu1-17/+19
2024-04-13aarch64: Add rcpc3 dependency on rcpc2 and rcpcAndrew Carlotti2-2/+3
2024-04-13aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-1/+1
2024-04-12rs6000: Add OPTION_MASK_POWER8 [PR101865]Will Schmidt7-9/+18
2024-04-12Regenerate opt.urlsTatsuyuki Ishi1-0/+2
2024-04-12aarch64: Avoid using mismatched ZERO ZA sizesRichard Sandiford1-8/+12
2024-04-12RISC-V: Fix Werror=sign-compare in riscv_validate_vector_typePan Li1-5/+5
2024-04-12RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_PPan Li1-1/+1
2024-04-11aarch64: Remove FMV features whose names may changeAndrew Carlotti1-12/+2
2024-04-11aarch64: Remove unsupported FMV featuresAndrew Carlotti1-38/+0
2024-04-11aarch64: Fix typo and make rdma/rdm alias for FMVAndrew Carlotti2-2/+7
2024-04-11aarch64: Fix FMV array iteration boundsAndrew Carlotti1-3/+5
2024-04-11aarch64: Reorder FMV feature prioritiesAndrew Carlotti1-11/+7
2024-04-11RISC-V: Bugfix ICE for the vector return arg in mode switchPan Li2-2/+40
2024-04-10target: missing -Whardened with -fcf-protection=none [PR114606]Marek Polacek1-1/+1
2024-04-10aarch64: Add support for _BitIntAndre Vieira1-0/+45
2024-04-10aarch64: Do not give ABI change diagnostics for _BitInt(N)Andre Vieira1-9/+52
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