riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-13	IBM zSystems: Fix predicate execute_operation	Stefan Schulze Frielinghaus	1	-2/+2
2023-02-13	RISC-V: Handle vlenb correctly in unwinding	Kito Cheng	1	-0/+7
2023-02-12	RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.	Jin Ma	1	-4/+6
2023-02-12	RISC-V: Add fixed-point support	Ju-Zhe Zhong	5	-13/+346
2023-02-12	RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support	Ju-Zhe Zhong	12	-56/+536
2023-02-12	RISC-V: Add vmadc/vmsbc C/C++ API support	Ju-Zhe Zhong	9	-1/+642
2023-02-12	RISC-V: Add vadc/vsbc C/C++ API support	Ju-Zhe Zhong	11	-7/+429
2023-02-12	RISC-V: allow vx instruction use "zero" as scalar register.	Ju-Zhe Zhong	1	-24/+33
2023-02-12	RISC-V: Add integer widening instructions	Ju-Zhe Zhong	12	-13/+539
2023-02-12	RISC-V: Add vmulh C/C++ support	Ju-Zhe Zhong	9	-0/+346
2023-02-12	RISC-V: Add vsext/vzext C/C++ intrinsic support	Ju-Zhe Zhong	10	-14/+401
2023-02-12	RISC-V: Add saturating Addition && Subtraction C/C++ Support	Ju-Zhe Zhong	7	-20/+320
2023-02-12	RISC-V: Add unary C/C++ API support	Ju-Zhe Zhong	9	-41/+108
2023-02-12	RISC-V: Fix VSETVL PASS bug in exception handling	Ju-Zhe Zhong	1	-3/+7
2023-02-10	RISC-V: Add binary vx C/C++ support	Ju-Zhe Zhong	11	-44/+591
2023-02-08	aarch64: Fix return_address_sign_ab_exception.C regression	Andrea Corallo	7	-10/+4
2023-02-07	Enable 512 bit vector for zen4	Jan Hubicka	1	-1/+1
2023-02-06	amdgcn: Pass -mstack-size through to runtime	Andrew Stubbs	1	-0/+18
2023-02-06	aarch64: Fix up bfmlal lane pattern [PR104921]	Alex Coplan	1	-1/+1
2023-02-06	LoongArch: Generate bytepick.[wd] for suitable bit operation pattern	Xi Ruoyao	2	-23/+45
2023-02-03	arm: [MVE] Add missing length=8 attribute	Christophe Lyon	1	-5/+9
2023-02-03	RISC-V: Remove unnecessary register class.	Monk Chiang	2	-14/+2
2023-02-03	RISC-V: Fix constraint bug for binary operation	Ju-Zhe Zhong	2	-61/+66
2023-02-03	RISC-V: Add RVV shift.vx C/C++ API support	Ju-Zhe Zhong	5	-1/+59
2023-02-02	amdgcn: Add instruction pattern for conditional shift operations	Paul-Antoine Arras	1	-0/+23
2023-02-02	amdgcn, libgomp: Manually allocated stacks	Andrew Stubbs	4	-111/+147
2023-02-02	arm: Fix MVE predicates synthesis [PR 108443]	Andre Vieira	12	-89/+117
2023-02-02	arm: Remove unnecessary zero-extending of MVE predicates before use [PR 107674]	Andre Vieira	2	-4/+9
2023-02-02	arm: Fix sign of MVE predicate mve_pred16_t [PR 107674]	Andre Vieira	1	-8/+8
2023-02-01	AArch64: Fix native detection in the presence of mandatory features which don...	Tamar Christina	1	-8/+0
2023-02-01	IBM zSystems: Save argument registers to the stack -mpreserve-args	Andreas Krebbel	2	-74/+184
2023-02-01	IBM zSystems: Make stack_tie to work with hard frame pointer	Andreas Krebbel	2	-11/+11
2023-02-01	RISC-V: Add integer binary vv C/C++ API support	Ju-Zhe Zhong	13	-8/+421
2023-01-31	PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1	Philipp Tomsich	1	-0/+1
2023-01-31	i386: Fix up ix86_convert_const_wide_int_to_broadcast [PR108599]	Jakub Jelinek	1	-1/+3
2023-01-31	i386: Fix up -Wuninitialized warnings in avx512erintrin.h [PR105593]	Jakub Jelinek	1	-12/+6
2023-01-31	RISC-V: Add indexed loads/stores C/C++ intrinsic support	Ju-Zhe Zhong	11	-33/+845
2023-01-30	Add support for x86_64--gnu- targets to build x86_64 gnumach/hurd	Flavio Cruz	1	-0/+40
2023-01-30	aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4	Philipp Tomsich	1	-1/+1
2023-01-30	Change AVX512FP16 to AVX512-FP16 in the document.	liuhongt	1	-1/+1
2023-01-29	aarch64: Correct the maximum shift amount for shifted operands	Philipp Tomsich	1	-1/+1
2023-01-28	RISC-V: Add vlse/vsse intrinsics support	Ju-Zhe Zhong	6	-14/+143
2023-01-28	RISC-V: Remove redundant attributes [NFC]	Ju-Zhe Zhong	1	-20/+0
2023-01-27	mips: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	ia64: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	alpha: Don't add crtfastmath.o for -shared	Richard Biener	1	-1/+1
2023-01-27	RISC-V: Fix vop_m overloaded C++ API name.	Ju-Zhe Zhong	1	-0/+4
2023-01-27	RISC-V: Add vlm/vsm C/C++ API intrinsics support	Ju-Zhe Zhong	7	-8/+86
2023-01-27	RISC-V: Finalize VSETVL PASS implementation	Ju-Zhe Zhong	2	-223/+737
2023-01-27	RISC-V: Fix bug of before_p function	Ju-Zhe Zhong	1	-1/+1