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AgeCommit message (Expand)AuthorFilesLines
2024-09-09i386: Use offsetable address constraint for double-word memory operandsUros Bizjak1-3/+3
2024-09-09hppa: Don't canonicalize operand order of scaled index addressesJohn David Anglin1-5/+4
2024-09-08x86-64: Don't use temp for argument in a TImode registerH.J. Lu1-2/+20
2024-09-07[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler modelZhao Dingyi1-3/+8
2024-09-07[PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e3...Jin Ma1-2/+2
2024-09-06rs6000,extend and document built-ins vec_test_lsbb_all_ones and vec_test_lsbb...Carl Love1-2/+10
2024-09-06aarch64: Use is_attribute_namespace_p and get_attribute_name inside aarch64_l...Andrew Pinski1-6/+2
2024-09-06AVR: Remove "Atmel" from header comment.Georg-Johann Lay22-27/+27
2024-09-05[PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halvesRaphael Moreira Zinsly1-0/+30
2024-09-05[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvementsRaphael Moreira Zinsly1-6/+132
2024-09-06Handle const0_operand for *avx2_pcmp<mode>3_1.liuhongt1-2/+7
2024-09-05[V2][RISC-V] Avoid unnecessary extensions after sCC insnsJeff Law1-5/+41
2024-09-05nvptx: Emit DECL and DEF linker markers for aliases [PR104957]Thomas Schwinge1-2/+4
2024-09-05i386: Support partial vectorized FMA for V2BF/V4BFLevy Hsu1-0/+80
2024-09-05i386: Support partial signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V...Levy Hsu2-35/+43
2024-09-05i386: Integrate BFmode for Enhanced Vectorization in ix86_preferred_simd_modeLevy Hsu1-0/+8
2024-09-04[PATCH 1/3] RISC-V: Improve codegen for negative repeating large constantsRaphael Moreira Zinsly1-8/+21
2024-09-04nvptx: Use 'enum ptx_version', 'enum ptx_isa' instead of 'int'Thomas Schwinge6-22/+37
2024-09-04Zen5 tuning part 5: update instruction latencies in x86-tune-costsJan Hubicka1-7/+21
2024-09-04CRIS: Add new peephole2 "lra_szext_decomposed_indir_plus"Hans-Peter Nilsson1-0/+45
2024-09-04RISC-V: Allow IMM operand for unsigned scalar .SAT_ADDPan Li2-3/+3
2024-09-03Zen5 tuning part 4: update reassocation widthJan Hubicka2-13/+20
2024-09-03Zen5 tuning part 3: fix typo in previous patchJan Hubicka1-1/+1
2024-09-03Zen5 tuning part 3: scheduler tweaksJan Hubicka3-3/+77
2024-09-03Zen5 tuning part 2: disable gather and scatterJan Hubicka1-6/+6
2024-09-03[PR target/115921] Improve reassociation for rv64Jeff Law1-4/+6
2024-09-03Zen5 tuning part 1: avoid FMA chainsJan Hubicka1-4/+5
2024-09-03i386: Fix vfpclassph non-optimizied intrinHaochen Jiang1-2/+2
2024-09-03SVE intrinsics: Fold constant operands for svmul.Jennifer Schmitz1-1/+14
2024-09-03SVE intrinsics: Fold constant operands for svdiv.Jennifer Schmitz3-3/+52
2024-09-03i386: Support partial vectorized V2BF/V4BF smaxminLevy Hsu1-0/+19
2024-09-03i386: Support partial vectorized V2BF/V4BF plus/minus/mult/div/sqrtLevy Hsu1-0/+37
2024-09-03RISC-V: Support form 1 of integer scalar .SAT_ADDPan Li3-0/+102
2024-09-03MIPS: Support vector reduc for MSAYunQiang Su4-0/+174
2024-09-02amdgcn: Remove TARGET_GCN5_PLUSAndrew Stubbs5-135/+59
2024-09-02amdgcn: Remove TARGET_GCN3Andrew Stubbs4-31/+7
2024-09-02amdgcn: remove gfx803 "Fiji" supportAndrew Stubbs7-51/+16
2024-09-01[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.Xianmiao Qu1-0/+5
2024-09-02i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2Levy Hsu2-0/+15
2024-09-02i386: Support vectorized BF16 sqrt with AVX10.2 instructionLevy Hsu1-5/+8
2024-09-02i386: Support vectorized BF16 smaxmin with AVX10.2 instructionsLevy Hsu1-0/+7
2024-09-02i386: Support vectorized BF16 FMA with AVX10.2 instructionsLevy Hsu1-1/+4
2024-09-02i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructionsLevy Hsu1-8/+41
2024-09-02i386: Optimize generate insn for AVX10.2 compareHu, Lin14-2/+51
2024-09-02i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructionsHaochen Jiang1-72/+21
2024-09-02RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64Pan Li1-53/+46
2024-08-31i386: Support read-modify-write memory operands in STV.Roger Sayle1-2/+4
2024-08-31AVR: Run pass avr-fuse-add a second time after pass_cprop_hardreg.Georg-Johann Lay2-0/+28
2024-08-31AVR: Tidy pass avr-fuse-add.Georg-Johann Lay4-43/+12
2024-08-31hppa: Enable PA 2.0 symbolic operands on ELF32 targetsJohn David Anglin3-27/+25
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