| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-09-15 | [ARM] Fix arm bootstrap failure due to -Werror=shift-negative-value | Kyrylo Tkachov | 1 | -4/+4 |
| 2015-09-15 | arm.c (TARGET_OPTION_PRINT): Define. | Christian Bruel | 1 | -0/+17 |
| 2015-09-15 | re PR target/52144 (ARM should support arm/thumb function attribute to permit... | Christian Bruel | 4 | -77/+51 |
| 2015-09-15 | [AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P | Alan Lawrence | 2 | -1/+8 |
| 2015-09-15 | [AArch64 array_mode 7/8] Combine the expanders using VSTRUCT:nregs | Alan Lawrence | 2 | -115/+26 |
| 2015-09-15 | [AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. | Alan Lawrence | 2 | -20/+10 |
| 2015-09-15 | [AArch64 array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size. | Alan Lawrence | 2 | -23/+13 |
| 2015-09-15 | [AArch64 array_mode 4/8] Remove EImode | Alan Lawrence | 3 | -12/+3 |
| 2015-09-15 | [AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md | Alan Lawrence | 2 | -22/+13 |
| 2015-09-15 | [AArch64 array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_s... | Alan Lawrence | 2 | -30/+34 |
| 2015-09-15 | [AArch64 array_mode 1/8] Rename vec_store_lanes<mode>_lane to aarch64_vec_sto... | Alan Lawrence | 1 | -6/+12 |
| 2015-09-15 | S/390: Add missing brackets. | Andreas Krebbel | 1 | -1/+1 |
| 2015-09-14 | [SPARC] Simplify const_all_ones_operand | Richard Sandiford | 1 | -25/+3 |
| 2015-09-14 | re PR target/67061 (sh64-elf: internal compiler error: in sh_find_set_of_reg,... | Oleg Endo | 1 | -15/+10 |
| 2015-09-14 | [AArch64] Handle literal pools for functions > 1 MiB in size. | Ramana Radhakrishnan | 5 | -4/+142 |
| 2015-09-14 | haswell.md: New file describing Haswell pipeline. | Yuri Rumyantsev | 3 | -7/+626 |
| 2015-09-13 | config.gcc (visium-*-*): Enable --with-cpu option, accept gr5 and gr6 as poss... | Olivier Hainque | 2 | -2/+20 |
| 2015-09-12 | remove STRUCT_VALUE macro | Trevor Saunders | 4 | -16/+0 |
| 2015-09-12 | pa.c (pa_output_move_double): Enhance to handle HIGH CONSTANT_P operands. | John David Anglin | 1 | -3/+14 |
| 2015-09-11 | Convert SPARC backend over to LRA. | David S. Miller | 4 | -54/+27 |
| 2015-09-11 | Remove separate movtf pattern - Use an iterator for all FP modes. | Ramana Radhakrishnan | 2 | -22/+4 |
| 2015-09-10 | nvptx.c (nvptx_expand_call): Add spacing. | Nathan Sidwell | 1 | -2/+5 |
| 2015-09-10 | rs6000.c (swap_web_entry): Update preceding commentary to simplify permute ma... | Bill Schmidt | 1 | -6/+198 |
| 2015-09-10 | re PR target/67506 ([SH]: error: unrecognizable insn when compiling texlive-b... | Oleg Endo | 1 | -0/+3 |
| 2015-09-10 | S/390: Don't use vgm for v1ti and v1tf. | Andreas Krebbel | 1 | -0/+5 |
| 2015-09-10 | S/390: Fix mode iterators vmal, vmah, and vmalh. | Andreas Krebbel | 1 | -15/+15 |
| 2015-09-10 | S/390: Add V1TImode to constant pool modes. | Andreas Krebbel | 1 | -2/+3 |
| 2015-09-10 | [ARM] PR 67439: Allow matching of *arm32_movhf when -mrestrict-it is on | Kyrylo Tkachov | 1 | -2/+3 |
| 2015-09-10 | arc-common.c: Remove references to A5. | Claudiu Zissulescu | 7 | -32/+10 |
| 2015-09-10 | arc.md (length): Fix attribute length for conditional executed instructions w... | Claudiu Zissulescu | 1 | -1/+5 |
| 2015-09-10 | [AArch64] Use logics_imm type for 2nd alternative of *and<mode>3nr_compare0 | Kyrylo Tkachov | 1 | -1/+1 |
| 2015-09-09 | nvptx.md (call_operation): Move bound out of loop. | Nathan Sidwell | 2 | -70/+68 |
| 2015-09-09 | nvptx.md (atomic_compare_and_swap<mode>): Use sel_truesi, not andsi. | Nathan Sidwell | 1 | -8/+6 |
| 2015-09-09 | [ARM][3/3] Expand mod by power of 2 | Kyrylo Tkachov | 2 | -1/+88 |
| 2015-09-09 | [AArch64][1/3] Expand signed mod by power of 2 using CSNEG | Kyrylo Tkachov | 2 | -1/+76 |
| 2015-09-09 | Fix PowerPC ICE due to secondary_reload ignoring reload replacements | Alan Modra | 1 | -1/+14 |
| 2015-09-08 | [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix | Alan Lawrence | 4 | -31/+69 |
| 2015-09-08 | [AArch64] Improve code generation for float16 vector code | Alan Lawrence | 3 | -20/+28 |
| 2015-09-08 | [AArch64] vreinterpret(q?), vget_(low|high), vld1(q?)_dup | Alan Lawrence | 1 | -0/+314 |
| 2015-09-08 | [AArch64] Implement vcvt_{,high_}f16_f32 | Alan Lawrence | 4 | -18/+35 |
| 2015-09-08 | [AArch64] vld{2,3,4}{,_lane,_dup}, vcombine, vcreate | Alan Lawrence | 4 | -9/+305 |
| 2015-09-08 | [AArch64] Add support for float16x{4,8}_t vectors/builtins | Alan Lawrence | 8 | -28/+137 |
| 2015-09-08 | [ARM] Remaining intrinsics | Alan Lawrence | 5 | -91/+501 |
| 2015-09-08 | [ARM] float16x8_t intrinsics in arm_neon.h | Alan Lawrence | 1 | -0/+257 |
| 2015-09-08 | [ARM] Add V8HFmode and float16x8_t type | Alan Lawrence | 5 | -2/+10 |
| 2015-09-08 | [ARM] float16x4_t intrinsics in arm_neon.h | Alan Lawrence | 1 | -0/+250 |
| 2015-09-07 | intelmic-mkoffload.c (prepare_target_image): Handle all non-alphanumeric char... | Ilya Verbin | 1 | -4/+5 |
| 2015-09-06 | cygming.h (SUBTARGET_OVERRIDE_OPTIONS): Do not warn. | Paolo Bonzini | 1 | -14/+1 |
| 2015-09-04 | re PR target/65210 ([avr] ICE: when using attributs 'address' and 'io_low') | Senthil Kumar Selvaraj | 1 | -0/+2 |
| 2015-09-04 | intelmic-mkoffload.c (prepare_target_image): Fix if the temp path contains a ... | Jonas Hahnfeld | 1 | -1/+1 |
