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AgeCommit message (Expand)AuthorFilesLines
2020-07-31AArch64: Add attributes according to flags in built-in functions [PR94442]xiezhiheng1-5/+116
2020-07-30[PATCH] RS6000 Add testlsbb by Byte operationsWill Schmidt5-0/+63
2020-07-31RISC-V: Add support for TLS stack protector canary accessCooper Qu4-0/+161
2020-07-30nvptx: Provide vec_set<mode> and vec_extract<vmode><mode> patternsRoger Sayle1-0/+80
2020-07-30Tune memcpy and memset for Zen cores.Martin Liska1-6/+6
2020-07-30Re-format zen memcpy/memset costs.Martin Liska1-10/+28
2020-07-29nvptx: Support floating point reciprocal instructionsRoger Sayle1-0/+9
2020-07-29arm: Enable no-writeback vldr.16/vstr.16.Joe Ramsay4-22/+88
2020-07-29config/mmix/mmix.h (NO_FUNCTION_CSE): Define to 1.Hans-Peter Nilsson1-0/+3
2020-07-29mmix.h (ASM_OUTPUT_EXTERNAL): Define to default_elf_asm_output_external.Hans-Peter Nilsson1-0/+5
2020-07-28nvptx: Support 16-bit shifts and extendqihi2Tom de Vries1-9/+16
2020-07-26rs6000: add option -mblock-ops-unaligned-vsxAaron Sawdey2-0/+14
2020-07-25config/mmix/mmix.c (TARGET_ASM_OUTPUT_IDENT): Override.Hans-Peter Nilsson1-0/+3
2020-07-25amdgcn: Enable TImodeAndrew Stubbs1-0/+15
2020-07-24aix: Support GCC64 for AIX 7.1.David Edelsohn3-50/+73
2020-07-24rs6000: Remove -mpower10 option (PR95907)Segher Boessenkool1-2/+1
2020-07-24revamp intelmic-mkoffload aux dump namesAlexandre Oliva1-10/+62
2020-07-24iDefine TARGET_OFFLOAD_OPTIONS for AArch64Matthias Klose1-0/+13
2020-07-24i386: Emit mfence_sse2 for -Os [PR95750]Uros Bizjak1-1/+2
2020-07-23rs6000: Rename function adjust_vectorization_costKewen Lin1-3/+3
2020-07-22rs6000: __builtin_mma_disassemble_acc() doesn't store elements correctly in L...Peter Bergner1-1/+2
2020-07-22Generation of adjusted ldp/stp for vector typesPrzemyslaw Wirkus4-6/+51
2020-07-21Add TARGET_LOWER_LOCAL_DECL_ALIGNMENT [PR95237]Sunil K Pandey2-3/+17
2020-07-21i386: Fix insn conditions of mfence patterns [PR95750]Uros Bizjak1-4/+2
2020-07-21MSP430: Remove do_no_relax_short_jumpsJozef Lawrynowicz3-41/+4
2020-07-21MSP430: Define extendqipsi2Jozef Lawrynowicz1-0/+9
2020-07-21MSP430: Define NO_FUNCTION_CSEJozef Lawrynowicz1-0/+5
2020-07-20rs6000: Define movsf_from_si2 to extract high part SF element from DImode[PR8...Xionghu Luo1-0/+31
2020-07-21mmix: support -fstack-usageHans-Peter Nilsson1-0/+16
2020-07-20sparc/sparc64: use crtendS.o for default-pie executables [PR96190]Sergei Trofimovich2-16/+4
2020-07-20i386: Use lock prefixed insn instead of MFENCE [PR95750]Uros Bizjak3-11/+17
2020-07-19vect: Support length-based partial vectors approachKewen Lin1-0/+5
2020-07-20mmix: When debug-dump, revert to "standard" pseudos for emitting integersHans-Peter Nilsson1-4/+31
2020-07-19x86: Add __cpuidex and include guard to <cpuid.h>H.J. Lu1-0/+12
2020-07-18x86-64: Define ASM_OUTPUT_ALIGNED_DECL_LOCALH.J. Lu1-0/+11
2020-07-17rs6000: Generate _Decimal128 to _Decimal32 hardware conversion instructionsPeter Bergner2-1/+18
2020-07-17x86: Rename VF_AVX512VL_VF1_128_256 to VF1_AVX512ER_128_256H.J. Lu1-8/+6
2020-07-17Arm: Add GCC_CPUINFO overrideTamar Christina1-1/+7
2020-07-17AArch64: Add GCC_CPUINFO overrideTamar Christina1-1/+6
2020-07-17AArch64: Fix bugs in -mcpu=native detection.Tamar Christina1-30/+103
2020-07-17amdgcn: Fix elf.h build issueAndrew Stubbs1-3/+8
2020-07-17vector creation from two parts of two vectors produces TBL rather than ins (P...Dmitrij Pochepko2-1/+78
2020-07-17__builtin_shuffle sometimes should produce zip1 rather than TBL (PR82199)Dmitrij Pochepko1-0/+57
2020-07-17AArch64: Add flags in built-in functions [PR94442]xiezhiheng3-568/+581
2020-07-17Fix PR96127Andreas Krebbel2-7/+12
2020-07-16i386: Additional peephole2 to use flags from CMPXCHG more [PR96189]Uros Bizjak1-0/+34
2020-07-16Reunify x86 stack checking implementationEric Botcazou1-206/+71
2020-07-16amdgcn: Handle early debug info in mkoffloadAndrew Stubbs1-13/+259
2020-07-15i386: Introduce peephole2 to use flags from CMPXCHG more [PR96189]Uros Bizjak1-0/+35
2020-07-15fix _mm512_{,mask_}cmp*_p[ds]_mask at -O0 [PR96174]Jakub Jelinek1-82/+82
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