| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2021-12-15 | Generate XXSPLTIW on power10. | Michael Meissner | 1 | -14/+14 |
| 2021-12-15 | Add LXVKQ support. | Michael Meissner | 1 | -0/+14 |
| 2021-11-08 | powerpc: Fix vsx_splat_v4si_di breakage on Power8. | David Edelsohn | 1 | -1/+1 |
| 2021-11-06 | powerpc: Fix vsx_splat_v4si in 32 bit mode | David Edelsohn | 1 | -2/+2 |
| 2021-10-27 | rs6000: Fold xxsel to vsel since they have same semantics | Xionghu Luo | 1 | -57/+0 |
| 2021-10-27 | rs6000: Fix wrong code generation for vec_sel [PR94613] | Xionghu Luo | 1 | -14/+46 |
| 2021-10-19 | rs6000: Remove unspecs for vec_mrghl[bhw] | Xionghu Luo | 1 | -10/+16 |
| 2021-08-25 | Make xxsplti*, xpermx, xxeval be vecperm type. | Michael Meissner | 1 | -13/+13 |
| 2021-08-20 | Move xx* builtins to vsx.md. | Michael Meissner | 1 | -0/+206 |
| 2021-08-03 | rs6000: Replace & by && | Segher Boessenkool | 1 | -1/+1 |
| 2021-07-19 | rs6000: Support [u]mul<mode>3_highpart for vector | Kewen Lin | 1 | -2/+2 |
| 2021-07-08 | rs6000: Support [u]mod<mode>3 for vector modulo insns | Kewen Lin | 1 | -2/+2 |
| 2021-06-09 | RS6000 Add 128-bit Binary Integer sign extend operations | Carl Love | 1 | -1/+82 |
| 2021-06-09 | rs6000, Add test 128-bit shifts for just the int128 type. | Carl Love | 1 | -18/+15 |
| 2021-06-09 | RS6000 add 128-bit Integer Operations part 1 | Carl Love | 1 | -0/+89 |
| 2021-03-30 | rs6000: Enable 32bit variable vec_insert [PR99718] | luoxhu@cn.ibm.com | 1 | -2/+2 |
| 2021-03-21 | rs6000: Fix some unexpected empty split conditions | Kewen Lin | 1 | -5/+5 |
| 2021-03-08 | rs6000: Fix invalid splits when using Altivec style addresses [PR98959] | Peter Bergner | 1 | -7/+14 |
| 2021-02-22 | rs6000: Use rldimi for vec init instead of shift + ior | Kewen Lin | 1 | -14/+8 |
| 2021-01-15 | rs6000, vector integer multiply/divide/modulo instructions | Carl Love | 1 | -50/+161 |
| 2021-01-04 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2020-11-02 | Add hint * too 2nd alternative of the 1st scratch in *vsx_extract_<mode>_stor... | Vladimir N. Makarov | 1 | -1/+1 |
| 2020-10-28 | VSX_EXTRACT fix | Carl Love | 1 | -1/+1 |
| 2020-10-22 | [PATCH, rs6000] VSX load/store rightmost element operations | Will Schmidt | 1 | -0/+18 |
| 2020-10-22 | [PATCH, rs6000] int128 sign extention instructions (partial prereq) | Will Schmidt | 1 | -0/+33 |
| 2020-10-22 | [RS6000] VSX_MM_SUFFIX | Alan Modra | 1 | -3/+3 |
| 2020-10-19 | rs6000: correct BE vextract_fp_from_short[hl] vperm masks | David Edelsohn | 1 | -2/+2 |
| 2020-09-14 | Rename mffgpr/mftgpr insn types and remove Power6 references. | Pat Haugen | 1 | -4/+4 |
| 2020-09-10 | Fix instruction types. | Pat Haugen | 1 | -3/+3 |
| 2020-08-18 | rs6000: Rename instruction xvcvbf16sp to xvcvbf16spn | Peter Bergner | 1 | -3/+3 |
| 2020-08-04 | rs6000, Add vector replace builtin support GCC maintainers: | Carl Love | 1 | -0/+60 |
| 2020-08-04 | rs6000 Add vector insert builtin support | Carl Love | 1 | -0/+110 |
| 2020-08-04 | rs6000, Update support for vec_extract | Carl Love | 1 | -0/+66 |
| 2020-07-30 | [PATCH] RS6000 Add testlsbb by Byte operations | Will Schmidt | 1 | -0/+39 |
| 2020-07-10 | RS6000, add VSX mask manipulation support | Carl Love | 1 | -0/+49 |
| 2020-07-08 | rs6000: Add len_load/len_store optab support | Kewen Lin | 1 | -0/+28 |
| 2020-06-24 | [PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin | Will Schmidt | 1 | -0/+10 |
| 2020-06-22 | rs6000: Rename future to power10 | Segher Boessenkool | 1 | -3/+3 |
| 2020-06-21 | rs6000: Add MMA built-in function definitions and test cases. | Peter Bergner | 1 | -0/+15 |
| 2020-05-18 | pr94833, fix vec_first_match_index for nulls | Carl Love | 1 | -2/+2 |
| 2020-05-11 | rs6000: Add xxgenpcvwm and xxgenpcvdm | Carl Love | 1 | -0/+32 |
| 2020-02-28 | Fix target/93937 | Michael Meissner | 1 | -22/+0 |
| 2020-02-27 | Fix PR target/93932 | Michael Meissner | 1 | -19/+71 |
| 2020-01-07 | Fix bad code of vector extract of PC-relative address with variable element #. | Michael Meissner | 1 | -4/+4 |
| 2020-01-01 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2019-11-12 | rs6000: Handle unordered for xscmpexp[dq]p without NaNs (PR92449) | Segher Boessenkool | 1 | -0/+12 |
| 2019-11-06 | vsx.md (xxswapd_<mode>): Add support for V2DF and V2DI modes. | Kelvin Nilsen | 1 | -0/+11 |
| 2019-11-01 | [rs6000] vector conversion RTL pattern update for diff unit size | Kewen Lin | 1 | -31/+83 |
| 2019-11-01 | [rs6000] vector conversion RTL pattern update for same unit size | Kewen Lin | 1 | -77/+28 |
