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path: root/gcc/config/rs6000/vsx.md
AgeCommit message (Expand)AuthorFilesLines
6 daysrs6000: Remove "+" constraint modifier from *vsx_le_perm_store_* insnsKewen Lin1-5/+5
6 daysrs6000: Fix vsx_le_perm_store_* splitters for !reload_completedKewen Lin1-11/+10
12 daysrs6000: Add TARGET_FLOAT128_HW guard for quad-precision insnsHaochen Gui1-10/+13
12 daysrs6000: Implement optab_isnormal for SFDF and IEEE128Haochen Gui1-0/+18
12 daysrs6000: Implement optab_isfinite for SFDF and IEEE128Haochen Gui1-0/+15
12 daysrs6000: Implement optab_isinf for SFDF and IEEE128Haochen Gui1-40/+18
2024-07-09rs6000, remove duplicated built-ins of vecmergl and vec_mergehCarl Love1-45/+0
2024-07-09rs6000, extend the current vec_{un,}signed{e,o} built-insCarl Love1-0/+84
2024-07-08rs6000: load high and low part of 128bit vector independently [PR110040]Jeevitha1-0/+17
2024-06-24rs6000: Eliminate unnecessary byte swaps for duplicated constant vector storeHaochen Gui1-0/+25
2024-06-20rs6000: Fix wrong RTL patterns for vector merge high/low word on LEKewen Lin1-12/+16
2024-03-07rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di [PR113950]Jeevitha1-2/+2
2024-01-09rs6000: Eliminate zext fed by vclzlsbb [PR111480]Kewen Lin1-23/+18
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-11-17rs6000: Fix regression cases caused 16-byte by pieces moveHaochen Gui1-0/+21
2023-10-02Replace UNSPEC_COPYSIGN with copysign RTLMichael Meissner1-4/+3
2023-09-17rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_indexAjit Kumar Agarwal1-3/+14
2023-08-16rs6000: Skip unnecessary vector extract for certain elements.Haochen Gui1-1/+15
2023-08-16rs6000: Generate mfvsrwz for all platforms and remove redundant zero extendHaochen Gui1-34/+78
2023-07-26rs6000, fix vec_replace_unaligned built-in argumentsCarl Love1-15/+19
2023-07-26rs6000: Correct vsx operands output for xxeval [PR110741]Kewen Lin1-1/+1
2023-06-28rs6000: Splat vector small V2DI constants with vspltisw and vupkhswHaochen Gui1-0/+24
2023-06-20rs6000: Add builtins for IEEE 128-bit floating point valuesCarl Love1-9/+16
2023-05-12rs6000: Change mode and insn condition for scalar insert exp instructionHaochen Gui1-6/+6
2023-05-12rs6000: Change mode and insn condition for scalar extract sig instructionHaochen Gui1-1/+1
2023-05-12rs6000: Change mode and insn condition for scalar extract exp instructionHaochen Gui1-4/+4
2023-04-11rs6000: correct vector sign extend builtins on Big EndianHaochen Gui1-77/+5
2023-04-09Do not generate vmaddfp and vnmsubfpMichael Meissner1-17/+17
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2022-12-01rs6000: Generates permute index directly for little endian targets (PR100866)Haochen Gui1-2/+2
2022-11-02rs6000: Byte reverse V8HI on Power8 by vector rotation.Xionghu Luo1-6/+15
2022-10-05rs6000: Rework vsx_extract_<mode>Segher Boessenkool1-43/+37
2022-10-05rs6000: Remove "wD" from *vsx_extract_<mode>_storeSegher Boessenkool1-2/+3
2022-06-14rs6000: Delete VS_scalarSegher Boessenkool1-75/+66
2022-03-29Allow vsx_extract_<mode> to use Altivec registers.Michael Meissner1-6/+3
2022-03-11Fix DImode to TImode sign extend issueMichael Meissner1-1/+1
2022-03-05Optimize signed DImode -> TImode on power10.Michael Meissner1-22/+61
2022-02-09rs6000: Correct function prototypes for vec_replace_unalignedBill Schmidt1-15/+10
2022-02-08rs6000: Add support for vmsumcud and vec_msumcBill Schmidt1-0/+13
2022-01-21Mark XXSPLTIW/XXSPLTIDP as prefixed -- PR 104136Michael Meissner1-1/+11
2022-01-16rs6000: Use known constant for GET_MODE_NUNITS and similarKewen Lin1-4/+12
2022-01-17rs6000: Split pattern for TI to V1TI move [PR103124]Haochen Gui1-0/+16
2022-01-13vect: Add bias parameter for partial vectorizationRobin Dapp1-1/+3
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-12-15Generate XXSPLTIW on power10.Michael Meissner1-14/+14
2021-12-15Add LXVKQ support.Michael Meissner1-0/+14
2021-11-08powerpc: Fix vsx_splat_v4si_di breakage on Power8.David Edelsohn1-1/+1
2021-11-06powerpc: Fix vsx_splat_v4si in 32 bit modeDavid Edelsohn1-2/+2
2021-10-27rs6000: Fold xxsel to vsel since they have same semanticsXionghu Luo1-57/+0
2021-10-27rs6000: Fix wrong code generation for vec_sel [PR94613]Xionghu Luo1-14/+46
generated by cgit v1.1 at 2024-08-27 13:59:53 +0000