index
:
riscv-gnu-toolchain/gcc.git
devel/analyzer
devel/autopar_devel
devel/autopar_europar_2021
devel/bypass-asm
devel/c++-contracts
devel/c++-coroutines
devel/c++-modules
devel/c++-name-lookup
devel/coarray_native
devel/fortran_unsigned
devel/gccgo
devel/gfortran-caf
devel/gimple-linterchange
devel/gomp-5_0-branch
devel/icpp2021
devel/ira-select
devel/ix86/evex512
devel/jlaw/crc
devel/loop-unswitch-support-switches
devel/lto-offload
devel/m2link
devel/modula-2
devel/mold-lto-plugin
devel/mold-lto-plugin-v2
devel/omp/gcc-10
devel/omp/gcc-11
devel/omp/gcc-12
devel/omp/gcc-13
devel/omp/gcc-14
devel/omp/gcc-9
devel/omp/ompd
devel/power-ieee128
devel/range-gen3
devel/ranger
devel/rust/master
devel/sphinx
devel/ssa-range
devel/subreg-coalesce
devel/unified-autovect
master
releases/egcs-1.0
releases/egcs-1.1
releases/gcc-10
releases/gcc-11
releases/gcc-12
releases/gcc-13
releases/gcc-14
releases/gcc-2.95
releases/gcc-2.95.2.1-branch
releases/gcc-3.0
releases/gcc-3.1
releases/gcc-3.2
releases/gcc-3.3
releases/gcc-3.4
releases/gcc-4.0
releases/gcc-4.1
releases/gcc-4.2
releases/gcc-4.3
releases/gcc-4.4
releases/gcc-4.5
releases/gcc-4.6
releases/gcc-4.7
releases/gcc-4.8
releases/gcc-4.9
releases/gcc-5
releases/gcc-6
releases/gcc-7
releases/gcc-8
releases/gcc-9
releases/libgcj-2.95
trunk
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
gcc
/
config
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2022-09-02
RISC-V: Implement TARGET_COMPUTE_MULTILIB
Kito Cheng
3
-2
/
+10
2022-09-01
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
zhongjuzhe
1
-0
/
+9
2022-09-01
RISC-V: Add csrr vlenb instruction.
zhongjuzhe
2
-22
/
+69
2022-09-01
RISC-V: Add RVV constraints.
zhongjuzhe
1
-0
/
+20
2022-09-01
RISC-V: Fix comment in riscv.h
zhongjuzhe
1
-1
/
+1
2022-09-01
RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN
zhongjuzhe
2
-7
/
+8
2022-08-29
RISC-V: Suppress -Wclass-memaccess warning
Kito Cheng
1
-1
/
+21
2022-08-29
RISC-V: Add RVV registers
zhongjuzhe
3
-19
/
+173
2022-08-29
RISC-V: Add RVV instructions classification
zhongjuzhe
1
-1
/
+99
2022-08-24
[RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md
Andrew Pinski
1
-4
/
+4
2022-08-24
[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand
Andrew Pinski
2
-3
/
+13
2022-08-24
[RISCV] Fix PR 106586: riscv32 vs ZBS
Andrew Pinski
3
-6
/
+14
2022-08-24
[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask
Andrew Pinski
3
-2
/
+15
2022-08-24
[RISCV] Use constraints/predicates instead of checking const_int directly for...
Andrew Pinski
3
-5
/
+14
2022-08-24
[RISCV] Add %~ to print w if TARGET_64BIT and use it
Andrew Pinski
3
-10
/
+30
2022-08-24
[RISCV] Add the list of operand modifiers to riscv.md too
Andrew Pinski
2
-1
/
+17
2022-08-24
[RISCV] Move iterators from sync.md to iterators.md
Andrew Pinski
2
-4
/
+7
2022-08-24
[RISCV] Move iterators from bitmanip.md to iterators.md
Andrew Pinski
2
-26
/
+26
2022-08-24
[RISCV] Move iterators from riscv.md to iterators.md
Andrew Pinski
2
-169
/
+212
2022-08-24
Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled
Andrew Pinski
1
-0
/
+24
2022-08-24
Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit
Andrew Pinski
1
-1
/
+1
2022-08-18
RISC-V: Standardize formatting of SFB ALU conditional move
Maciej W. Rozycki
1
-2
/
+2
2022-08-18
RISC-V: Add runtime invariant support
zhongjuzhe
7
-68
/
+142
2022-08-16
RISC-V: Support zfh and zfhmin extension
Kito Cheng
4
-9
/
+92
2022-08-16
RISC-V: Support _Float16 type.
Kito Cheng
4
-18
/
+208
2022-08-04
[RSIC-V] Fix 32bit riscv with zbs extension enabled
Andrew Pinski
1
-1
/
+1
2022-07-28
RISC-V: Split unordered FP comparisons into individual RTL insns
Maciej W. Rozycki
1
-33
/
+36
2022-07-27
RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>'
Maciej W. Rozycki
1
-1
/
+1
2022-07-27
RISC-V: Add RTX costs for `if_then_else' expressions
Maciej W. Rozycki
1
-0
/
+27
2022-06-20
RISC-V: Fix a bug that is the CMO builtins are missing parameter
yulong
3
-10
/
+10
2022-06-17
RISC-V: Supress warning for comparison of integer expressions of different si...
Kito Cheng
1
-1
/
+1
2022-06-14
RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w
Philipp Tomsich
1
-0
/
+44
2022-06-14
RISC-V: add consecutive_bits_operand predicate
Philipp Tomsich
1
-0
/
+11
2022-06-13
RISC-V: Reset the length to the default of 4 for FP comparisons
Maciej W. Rozycki
1
-2
/
+0
2022-06-09
RISC-V: Use a tab rather than space with FSFLAGS
Maciej W. Rozycki
1
-2
/
+2
2022-06-02
RISC-V: bitmanip: improve constant-loading for (1ULL << 31) in DImode
Philipp Tomsich
2
-7
/
+13
2022-05-25
RISC-V: Don't unconditionally add m,a,f,d in arch-canonicalize
Simon Cook
1
-1
/
+1
2022-05-24
RISC-V: Cache Management Operation instructions
ShiYulong
5
-0
/
+98
2022-05-24
RISC-V: Add mininal support for Zicbo[mzp]
ShiYulong
2
-0
/
+11
2022-05-24
RISC-V: Inhibit FP <--> int register moves via tune param
Vineet Gupta
1
-0
/
+9
2022-05-23
RISC-V: Enable TARGET_SUPPORTS_WIDE_INT
Vineet Gupta
3
-1
/
+9
2022-05-23
RISC-V: Fix canonical extension order (K and J)
Tsukasa OI
1
-1
/
+1
2022-05-13
RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO
Philipp Tomsich
1
-0
/
+5
2022-05-11
opts: do not allow Separate+Joined ending with =
Martin Liska
1
-1
/
+1
2022-05-10
RISC-V: Provide `fmin'/`fmax' RTL patterns
Maciej W. Rozycki
1
-0
/
+22
2022-05-09
RISC-V: Fix wrong expansion for arch-canonicalize
Kito Cheng
1
-3
/
+5
2022-04-11
RISC-V: Support -misa-spec for arch-canonicalize and multilib-generator. [PR1...
Kito Cheng
2
-9
/
+37
2022-04-11
RISC-V: Sync arch-canonicalize and riscv-common.cc
Kito Cheng
1
-21
/
+37
2022-03-21
RISC-V: Implement misc macro for vector extensions.
Kito Cheng
3
-5
/
+40
2022-03-16
RISC-V: Handle combine extension in canonical ordering.
LiaoShihua
1
-0
/
+1
[next]