riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-03-19	RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]	Edwin Lu	1	-1/+2
2024-03-18	[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P	Mary Bennett	5	-1/+50
2024-03-18	[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.	Chen Jiawei	5	-1/+174
2024-03-15	Regenerate opt.urls	YunQiang Su	1	-1/+1
2024-03-12	RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]	Pan Li	1	-5/+5
2024-03-08	RISC-V: Fix ICE in riscv vector costs	demin.han	1	-0/+2
2024-03-07	RISC-V: Refactor expand_vec_cmp [NFC]	demin.han	2	-31/+15
2024-03-06	RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].	Robin Dapp	1	-48/+48
2024-03-06	RISC-V: Adjust vec unit-stride load/store costs.	Robin Dapp	2	-10/+86
2024-03-06	[PR target/113001] Fix incorrect operand swapping in conditional move	Jeff Law	1	-2/+0
2024-03-05	RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]	Pan Li	1	-4/+0
2024-03-04	Regenerate opt.urls	Mark Wielaard	1	-1/+1
2024-03-01	[14 regression] Fix insn types in risc-v port	Jeff Law	1	-14/+14
2024-03-01	RISC-V: Add riscv_vector_cc function attribute	xuli	1	-8/+47
2024-03-01	RISC-V: Introduce gcc option mrvv-vector-bits for RVV	Pan Li	6	-42/+45
2024-02-29	RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64	Kito Cheng	1	-0/+9
2024-02-23	RISC-V: Fix vec_init for simple sequences [PR114028].	Robin Dapp	1	-1/+24
2024-02-23	RISC-V: Point our Python scripts at python3	Palmer Dabbelt	2	-2/+2
2024-02-22	RISC-V: Upgrade RVV intrinsic version to 0.12	Pan Li	1	-1/+1
2024-02-21	RISC-V: Enable assert for insn_has_dfa_reservation	Edwin Lu	1	-2/+0
2024-02-21	RISC-V: Add vector related pipelines	Edwin Lu	3	-126/+145
2024-02-21	RISC-V: Add non-vector types to dfa pipelines	Edwin Lu	8	-69/+117
2024-02-19	RISC-V: Suppress the vsetvl fusion for conflict successors	Juzhe-Zhong	1	-0/+25
2024-02-16	RISC-V: Fix *sge<u>_<X:mode><GPR:mode> pattern	Kito Cheng	1	-1/+1
2024-02-16	RISC-V: Add new option -march=help to print all supported extensions	Kito Cheng	4	-2/+26
2024-02-13	Re: [PATCH] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_A...	Monk Chiang	1	-1/+1
2024-02-12	RISC-V: Fix misspelled term args in error_at message	Pan Li	1	-1/+2
2024-02-08	RISC-V: Bugfix for RVV overloaded intrinsic ICE in function checker	Pan Li	1	-4/+13
2024-02-07	RISC-V: Bugfix for RVV overloaded intrinisc ICE when empty args	Pan Li	3	-6/+22
2024-02-06	RISC-V: Fix infinite compilation of VSETVL PASS	Juzhe-Zhong	1	-5/+4
2024-02-06	riscv: Fix compiler warning in thead.cc	Christoph Müllner	1	-1/+2
2024-02-04	RISC-V: Add sifive-p450, sifive-p67 to -mcpu	Monk Chiang	1	-0/+9
2024-02-04	RISC-V: Support scheduling for sifive p400 series	Monk Chiang	6	-1/+196
2024-02-04	[committed] Reasonably handle SUBREGs in risc-v cost modeling	Jeff Law	1	-7/+11
2024-02-03	RISC-V: Expand VLMAX scalar move in reduction	Juzhe-Zhong	1	-5/+7
2024-02-02	Revert "RISC-V: Allow LICM hoist POLY_INT configuration code sequence"	Lehua Ding	1	-5/+4
2024-02-02	RISC-V: Allow LICM hoist POLY_INT configuration code sequence	Juzhe-Zhong	1	-4/+5
2024-02-02	RISC-V: Cleanup the comments for the psabi	Pan Li	1	-12/+9
2024-02-02	RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS	Juzhe-Zhong	1	-0/+64
2024-02-01	RISC-V: Support scheduling for sifive p600 series	Monk Chiang	9	-12/+214
2024-02-01	RISC-V: Add minimal support for 7 new unprivileged extensions	Monk Chiang	1	-0/+14
2024-01-31	Revert "RISC-V: Add non-vector types to dfa pipelines"	Edwin Lu	6	-102/+66
2024-01-31	Revert "RISC-V: Add vector related pipelines"	Edwin Lu	3	-145/+126
2024-01-31	Revert "RISC-V: Enable assert for insn_has_dfa_reservation"	Edwin Lu	1	-0/+2
2024-01-31	RISC-V: Enable assert for insn_has_dfa_reservation	Edwin Lu	1	-2/+0
2024-01-31	RISC-V: Add vector related pipelines	Edwin Lu	3	-126/+145
2024-01-31	RISC-V: Add non-vector types to dfa pipelines	Edwin Lu	6	-66/+102
2024-01-31	RISC-V: Fix VSETLV PASS compile-time issue	Juzhe-Zhong	1	-124/+60
2024-01-30	RISC-V: Bugfix for vls mode aggregated in GPR calling convention	Pan Li	1	-0/+78
2024-01-30	riscv: Move UNSPEC_XTHEAD* from unspecv to unspec	Christoph Müllner	1	-4/+4