riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-10-24	RISC-V: Fix REG_CLASS_CONTENTS.	Ju-Zhe Zhong	1	-1/+1
2022-10-21	RISC-V: Add type attribute for atomic instructions.	Monk Chiang	2	-6/+11
2022-10-21	RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.	Ju-Zhe Zhong	11	-1/+549
2022-10-21	RISC-V: Add RVV intrinsic basic framework.	Ju-Zhe Zhong	5	-81/+1063
2022-10-17	RISC-V: Fix format[NFC]	Ju-Zhe Zhong	1	-1/+1
2022-10-17	RISC-V: Reorganize mangle_builtin_type.[NFC]	Ju-Zhe Zhong	1	-13/+13
2022-10-12	RISC-V: Remove TUPLE size macro define. [NFC]	Ju-Zhe Zhong	1	-3/+0
2022-10-12	RISC-V: Apply clang-format for riscv-vector-builtins.* [NFC]	Ju-Zhe Zhong	3	-7/+6
2022-10-12	RISC-V: Refine register_builtin_types function. [NFC]	Ju-Zhe Zhong	2	-40/+50
2022-10-12	RISC-V: Move function place to make it looks better. [NFC]	Ju-Zhe Zhong	2	-19/+19
2022-10-11	RISC-V: move struct vector_type_info from .h to .cc and change "user_name" ...	Ju-Zhe Zhong	3	-25/+25
2022-10-11	RISC-V: Add missing vsetvl instruction type.	Ju-Zhe Zhong	1	-1/+2
2022-10-10	RISC-V: Add newline to the end of file [NFC]	Kito Cheng	1	-1/+1
2022-10-05	RISC-V: Introduce RVV header to enable builtin types	Ju-Zhe Zhong	9	-13/+210
2022-10-05	RISC-V: remove deprecate pic code model macro	Vineet Gupta	1	-5/+0
2022-09-30	RISC-V: Support -fexcess-precision=16	Palmer Dabbelt	1	-0/+1
2022-09-30	RISC-V: Add '-m[no]-csr-check' option in gcc.	Jiawei	2	-0/+11
2022-09-29	RISC-V: Add ABI-defined RVV types.	Ju-Zhe Zhong	8	-1/+828
2022-09-23	RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand	Vineet Gupta	1	-6/+7
2022-09-23	RISC-V: Add RVV machine modes.	zhongjuzhe	1	-0/+141
2022-09-23	RISC-V: Support poly move manipulation and selftests.	zhongjuzhe	5	-5/+550
2022-09-05	RISC-V: Fix division instructions for `m` with `zmmul` extension.	Kito Cheng	2	-7/+3
2022-09-05	RISC-V: Support Zmmul extension	LiaoShihua	4	-16/+26
2022-09-02	d: Fix #error You must define PREFERRED_DEBUGGING_TYPE if DWARF is not supported	Iain Buclaw	4	-8/+25
2022-09-02	RISC-V: Implement TARGET_COMPUTE_MULTILIB	Kito Cheng	3	-2/+10
2022-09-01	RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE	zhongjuzhe	1	-0/+9
2022-09-01	RISC-V: Add csrr vlenb instruction.	zhongjuzhe	2	-22/+69
2022-09-01	RISC-V: Add RVV constraints.	zhongjuzhe	1	-0/+20
2022-09-01	RISC-V: Fix comment in riscv.h	zhongjuzhe	1	-1/+1
2022-09-01	RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN	zhongjuzhe	2	-7/+8
2022-08-29	RISC-V: Suppress -Wclass-memaccess warning	Kito Cheng	1	-1/+21
2022-08-29	RISC-V: Add RVV registers	zhongjuzhe	3	-19/+173
2022-08-29	RISC-V: Add RVV instructions classification	zhongjuzhe	1	-1/+99
2022-08-24	[RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md	Andrew Pinski	1	-4/+4
2022-08-24	[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand	Andrew Pinski	2	-3/+13
2022-08-24	[RISCV] Fix PR 106586: riscv32 vs ZBS	Andrew Pinski	3	-6/+14
2022-08-24	[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask	Andrew Pinski	3	-2/+15
2022-08-24	[RISCV] Use constraints/predicates instead of checking const_int directly for...	Andrew Pinski	3	-5/+14
2022-08-24	[RISCV] Add %~ to print w if TARGET_64BIT and use it	Andrew Pinski	3	-10/+30
2022-08-24	[RISCV] Add the list of operand modifiers to riscv.md too	Andrew Pinski	2	-1/+17
2022-08-24	[RISCV] Move iterators from sync.md to iterators.md	Andrew Pinski	2	-4/+7
2022-08-24	[RISCV] Move iterators from bitmanip.md to iterators.md	Andrew Pinski	2	-26/+26
2022-08-24	[RISCV] Move iterators from riscv.md to iterators.md	Andrew Pinski	2	-169/+212
2022-08-24	Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled	Andrew Pinski	1	-0/+24
2022-08-24	Fix PR 106600: __builtin_bswap32 is not hooked up for ZBB for 32bit	Andrew Pinski	1	-1/+1
2022-08-18	RISC-V: Standardize formatting of SFB ALU conditional move	Maciej W. Rozycki	1	-2/+2
2022-08-18	RISC-V: Add runtime invariant support	zhongjuzhe	7	-68/+142
2022-08-16	RISC-V: Support zfh and zfhmin extension	Kito Cheng	4	-9/+92
2022-08-16	RISC-V: Support _Float16 type.	Kito Cheng	4	-18/+208
2022-08-04	[RSIC-V] Fix 32bit riscv with zbs extension enabled	Andrew Pinski	1	-1/+1