index
:
riscv-gnu-toolchain/gcc.git
devel/analyzer
devel/autopar_devel
devel/autopar_europar_2021
devel/bypass-asm
devel/c++-contracts
devel/c++-coroutines
devel/c++-modules
devel/c++-name-lookup
devel/coarray_native
devel/fortran_unsigned
devel/gccgo
devel/gfortran-caf
devel/gimple-linterchange
devel/gomp-5_0-branch
devel/icpp2021
devel/ira-select
devel/ix86/evex512
devel/jlaw/crc
devel/loop-unswitch-support-switches
devel/lto-offload
devel/m2link
devel/modula-2
devel/mold-lto-plugin
devel/mold-lto-plugin-v2
devel/omp/gcc-10
devel/omp/gcc-11
devel/omp/gcc-12
devel/omp/gcc-13
devel/omp/gcc-14
devel/omp/gcc-9
devel/omp/ompd
devel/power-ieee128
devel/range-gen3
devel/ranger
devel/rust/master
devel/sphinx
devel/ssa-range
devel/subreg-coalesce
devel/unified-autovect
master
releases/egcs-1.0
releases/egcs-1.1
releases/gcc-10
releases/gcc-11
releases/gcc-12
releases/gcc-13
releases/gcc-14
releases/gcc-2.95
releases/gcc-2.95.2.1-branch
releases/gcc-3.0
releases/gcc-3.1
releases/gcc-3.2
releases/gcc-3.3
releases/gcc-3.4
releases/gcc-4.0
releases/gcc-4.1
releases/gcc-4.2
releases/gcc-4.3
releases/gcc-4.4
releases/gcc-4.5
releases/gcc-4.6
releases/gcc-4.7
releases/gcc-4.8
releases/gcc-4.9
releases/gcc-5
releases/gcc-6
releases/gcc-7
releases/gcc-8
releases/gcc-9
releases/libgcj-2.95
trunk
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
gcc
/
config
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2021-08-16
RISC-V: Allow multi-lib build with different code model
Kito Cheng
1
-30
/
+56
2021-07-13
docs: Add 'S' to Machine Constraints for RISC-V
Kito Cheng
1
-2
/
+1
2021-06-22
RISC-V: Add tune info for T-HEAD C906.
Jojo R
1
-0
/
+14
2021-05-25
RISC-V: Pass -mno-relax to assembler
Kito Cheng
1
-0
/
+1
2021-05-18
Use startswith in targets.
Martin Liska
1
-1
/
+1
2021-05-05
RISC-V: Generate helpers for cbranch4.
Christoph Muellner
2
-12
/
+5
2021-04-29
RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions it...
Geng Qi
1
-2
/
+2
2021-04-29
RISC-V: Add patterns for builtin overflow.
LevyHsu
3
-0
/
+257
2021-04-14
d: Add TARGET_D_REGISTER_CPU_TARGET_INFO
Iain Buclaw
3
-1
/
+49
2021-03-26
d: Define IN_TARGET_CODE in all machine-specific D language files.
Iain Buclaw
1
-0
/
+2
2021-03-23
RISC-V: Fix riscv_subword() for big endian
Marcus Comstedt
1
-1
/
+1
2021-03-23
RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md
Marcus Comstedt
2
-35
/
+40
2021-03-23
RISC-V: Fix trampoline generation on big endian
Marcus Comstedt
1
-4
/
+15
2021-03-23
RISC-V: Add riscv{32,64}be with big endian as default
Marcus Comstedt
5
-3
/
+14
2021-03-23
RISC-V: Support -mlittle-endian and -mbig-endian
Marcus Comstedt
5
-2
/
+18
2021-03-22
PR target/99702: Check RTL type before get value
Kito Cheng
1
-1
/
+1
2021-03-19
PR target/99314: Fix integer signedness issue for cpymem pattern expansion.
Sinan Lin
1
-11
/
+13
2021-02-13
RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.
Levy Hsu
2
-7
/
+49
2021-02-13
RISC-V: Shorten memrefs improvement, partial fix 97417.
Jim Wilson
1
-8
/
+11
2021-01-19
RISC-V: The 'multilib-generator' enhancement.
Geng Qi
2
-6
/
+20
2021-01-08
RISC-V: Implement new style of architecture extension test macros.
Kito Cheng
2
-0
/
+37
2021-01-08
RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h
Kito Cheng
2
-1
/
+93
2021-01-04
Update copyright years.
Jakub Jelinek
26
-26
/
+26
2020-12-24
RISC-V: Fix python3 compatibility for multilib-generator
Kito Cheng
1
-1
/
+1
2020-12-16
opts: Remove all usages of Report keyword.
Martin Liska
1
-11
/
+11
2020-12-10
RISC-V: Explicitly call python when using multilib generator
Simon Cook
1
-1
/
+2
2020-12-03
RISC-V: Canonicalize --with-arch
Kito Cheng
2
-75
/
+110
2020-11-30
RISC-V: Always define MULTILIB_DEFAULTS
Kito Cheng
2
-51
/
+9
2020-11-18
RISC-V: Support version controling for ISA standard extensions
Kito Cheng
3
-1
/
+35
2020-11-18
RISC-V: Support zicsr and zifencei extension for -march.
Kito Cheng
3
-2
/
+12
2020-11-13
PR target/97682 - Fix to reuse t1 register between call address and epilogue.
Monk Chiang
2
-12
/
+17
2020-11-13
Asan changes for RISC-V.
Jim Wilson
1
-0
/
+16
2020-11-02
RISC-V: Add configure option: --with-multilib-generator to flexible config mu...
Kito Cheng
2
-1
/
+10
2020-10-22
RISC-V: Extend syntax for the multilib-generator
Kito Cheng
1
-7
/
+102
2020-10-16
RISC-V: Handle implied extension in multilib-generator
Kito Cheng
1
-4
/
+20
2020-10-15
RISC-V: Add support for -mcpu option.
Kito Cheng
6
-52
/
+139
2020-09-29
RISC-V: Define __riscv_cmodel_medany for PIC mode.
Kito Cheng
1
-3
/
+6
2020-09-17
RISC-V: fix a typo in riscv.h
Yeting Kuo
1
-1
/
+1
2020-07-31
RISC-V: Add support for TLS stack protector canary access
Cooper Qu
4
-0
/
+161
2020-07-09
RISC-V: Implement __builtin_thread_pointer
Kito Cheng
1
-0
/
+8
2020-07-09
RISC-V: Disable remove unneeded save-restore call optimization if there are a...
Kito Cheng
1
-0
/
+6
2020-07-02
RISC-V: Handle multi-letter extension for multilib-generator
Kito Cheng
1
-8
/
+22
2020-06-22
RISC-V: Normalize arch string in driver time
Kito Cheng
1
-1
/
+5
2020-06-22
RISC-V: Fix compilation failed for frflags builtin in C++ mode
Kito Cheng
2
-2
/
+5
2020-06-16
RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]
Kito Cheng
1
-1
/
+4
2020-06-15
RISC-V: Suppress warning for signed and unsigned integer comparison.
Kito Cheng
1
-3
/
+3
2020-06-10
RISC-V: Unify the output asm pattern between gpr_save and gpr_restore pattern.
Kito Cheng
4
-18
/
+3
2020-06-10
RISC-V: Describe correct USEs for gpr_save pattern [PR95252]
Kito Cheng
5
-5
/
+109
2020-05-30
RISC-V: Optimize si to di zero-extend followed by left shift.
Jim Wilson
1
-0
/
+22
2020-05-19
RISC-V: Handle implied extension for -march parser.
Kito Cheng
2
-2
/
+7
[next]