| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-03-25 | RISC-V: Allow RVV intrinsic when function target("arch=+v") | Pan Li | 1 | -4/+0 |
| 2024-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2023-07-27 | RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic. | Pan Li | 1 | -51/+0 |
| 2023-01-16 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2022-10-05 | RISC-V: Introduce RVV header to enable builtin types | Ju-Zhe Zhong | 1 | -0/+100 |
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index : riscv-gnu-toolchain/gcc.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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