riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-12-02	RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.	yulong	1	-1/+2
2024-11-29	[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.	Mariam Arutunian	1	-0/+4
2024-11-29	RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.	yulong	1	-1/+3
2024-11-29	__builtin_prefetch fixes [PR117608]	Jakub Jelinek	1	-1/+2
2024-11-19	[RISC-V][PR target/117649] Fix branch on masked values splitter	Jeff Law	1	-1/+1
2024-10-19	[PATCH 4/7] RISC-V: Honour -mrvv-max-lmul in riscv_vector::expand_block_move	Craig Blackmore	1	-10/+2
2024-10-12	[RISC-V] Avoid unnecessary extensions when value is already extended	Jivan Hakobyan	1	-2/+18
2024-10-09	RISC-V: Optimize branches with shifted immediate operands	Jovan Vukic	1	-0/+32
2024-10-08	RISC-V: Implement scalar SAT_TRUNC for signed integer	Pan Li	1	-0/+30
2024-09-30	RISC-V: Implement scalar SAT_SUB for signed integer	Pan Li	1	-0/+11
2024-09-18	[PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern i...	Jin Ma	1	-7/+9
2024-09-16	riscv: Fix duplicate assmbler label in @tlsdesc<mode> insn	Andreas Schwab	1	-8/+7
2024-09-04	RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD	Pan Li	1	-2/+2
2024-09-03	[PR target/115921] Improve reassociation for rv64	Jeff Law	1	-4/+6
2024-09-03	RISC-V: Support form 1 of integer scalar .SAT_ADD	Pan Li	1	-0/+11
2024-08-27	RISC-V: Support IMM for operand 1 of ussub pattern	Pan Li	1	-1/+1
2024-08-26	RISC-V: Support IMM for operand 0 of ussub pattern	Pan Li	1	-1/+1
2024-08-18	RISC-V: Implement the quad and oct .SAT_TRUNC for scalar	Pan Li	1	-0/+20
2024-08-17	[RISC-V][PR target/116282] Stabilize pattern conditions	Jeff Law	1	-8/+8
2024-08-15	RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins	Vineet Gupta	1	-0/+63
2024-08-09	RISC-V: Small stack tie changes	Raphael Moreira Zinsly	1	-1/+1
2024-08-08	RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx	Christoph Müllner	1	-2/+2
2024-07-23	RISC-V: Implement the .SAT_TRUNC for scalar	Pan Li	1	-0/+10
2024-07-15	RISC-V: Implement locality for __builtin_prefetch	Monk Chiang	1	-3/+7
2024-07-15	RISC-V: Add md files for vector BFloat16	Feng Wang	1	-1/+12
2024-07-12	[RISC-V] Avoid unnecessary sign extension after memcmp	Jeff Law	1	-2/+12
2024-07-11	[to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined s...	Jeff Law	1	-4/+24
2024-06-29	[to-be-committed,RISC-V,V4] movmem for RISCV with V extension	Sergei Lewis	1	-0/+22
2024-06-25	[PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension	Sergei Lewis	1	-1/+6
2024-06-24	[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension	Sergei Lewis	1	-2/+7
2024-06-08	RISC-V: Implement .SAT_SUB for unsigned scalar int	Pan Li	1	-0/+11
2024-06-05	RISC-V: Add Zfbfmin extension	Xiao Zeng	1	-7/+42
2024-05-28	[to-be-committed] [RISC-V] Some basic patterns for zbkb code generation	Lyut Nersisyan	1	-3/+6
2024-05-26	[to-be-committed][RISC-V] Reassociate constants in logical ops	Lyut Nersisyan	1	-0/+28
2024-05-24	[to-be-committed,v2,RISC-V] Use bclri in constant synthesis	Jeff Law	1	-1/+1
2024-05-18	[to-be-committed,RISC-V] Improve some shift-add sequences	Jeff Law	1	-0/+56
2024-05-18	RISC-V: Fix "Nan-box the result of movbf on soft-bf16"	Xiao Zeng	1	-14/+5
2024-05-18	RISC-V: Implement IFN SAT_ADD for both the scalar and vector	Pan Li	1	-0/+11
2024-05-15	[v2,1/2] RISC-V: Add cmpmemsi expansion	Christoph Müllner	1	-0/+15
2024-05-14	[to-be-committed,RISC-V] Remove redundant AND in shift-add sequence	Jeff Law	1	-0/+25
2024-05-14	RISC-V: avoid LUI based const materialization ... [part of PR/106265]	Vineet Gupta	1	-0/+40
2024-05-14	[PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero	Christoph Müllner	1	-0/+24
2024-05-13	Revert "[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension"	Jeff Law	1	-23/+0
2024-05-13	[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension	Sergei Lewis	1	-0/+23
2024-05-08	[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16	Xiao Zeng	1	-1/+11
2024-05-08	RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4	Christoph Müllner	1	-8/+17
2024-05-08	RISC-V: Add zero_extract support for rv64gc	Christoph Müllner	1	-0/+30
2024-05-08	RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2	Christoph Müllner	1	-4/+5
2024-05-06	[RISC-V] Add support for _Bfloat16	Xiao Zeng	1	-12/+12
2024-05-02	[committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits	Jeff Law	1	-31/+34