riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-10-05	RISC-V: Fix -fsignaling-nans for glibc testsuite.	Andrew Waterman	1	-6/+28
2018-09-26	RISC-V: Add missing negate patterns.	Jim Wilson	1	-3/+38
2018-08-28	Rewrite pic.md to improve medany and pic code size.	Jim Wilson	1	-3/+13
2018-07-02	RISC-V: Fix interrupt support for -g.	Jim Wilson	1	-3/+6
2018-06-30	RISC-V: Add patterns to convert AND mask to two shifts.	Jim Wilson	1	-0/+32
2018-06-06	RISC-V: Add interrupt attribute modes.	Jim Wilson	1	-0/+12
2018-06-04	RISC-V: Don't clobber retval when __builtin_eh_return called.	Jim Wilson	1	-2/+17
2018-05-25	RISC-V: Add interrupt attribute support.	Jim Wilson	1	-2/+11
2018-05-16	RISC-V: Minor pattern name cleanup.	Jim Wilson	1	-4/+4
2018-04-02	RISC-V: Fix for combine bug with shift and AND operations.	Jim Wilson	1	-4/+132
2018-01-10	RISC-V: Add naked function support.	Kito Cheng	1	-1/+3
2018-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2018-01-02	RISC-V: Fix for icache flush issue on multicore processors.	Andrew Waterman	1	-0/+6
2017-11-29	Riscv patterns to optimize away some redundant zero/sign extends.	Jim Wilson	1	-0/+43
2017-11-07	RISC-V: Implement movmemsi	Andrew Waterman	1	-0/+13
2017-11-05	RISC-V: Emit "i" suffix for instructions with immediate operands	Michael Clark	1	-18/+18
2017-10-25	RISC-V: Add Sign/Zero extend patterns for PIC loads	Palmer Dabbelt	1	-0/+3
2017-09-15	Turn TRULY_NOOP_TRUNCATION into a hook	Richard Sandiford	1	-1/+2
2017-05-05	RISC-V: Unify indention in riscv.md	Kito Cheng	1	-272/+287
2017-02-06	RISC-V Port: gcc	Palmer Dabbelt	1	-0/+2079