| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-12-23 | RISC-V: Support vle.v/vse.v intrinsics | Ju-Zhe Zhong | 1 | -2/+8 |
| 2022-12-19 | RISC-V: Support VSETVL PASS for RVV support | Ju-Zhe Zhong | 1 | -8/+94 |
| 2022-12-19 | RISC-V: Change vlmul printing rule | Ju-Zhe Zhong | 1 | -1/+1 |
| 2022-12-02 | RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst | Ju-Zhe Zhong | 1 | -1/+2 |
| 2022-12-02 | RISC-V: Add attributes for VSETVL PASS | Ju-Zhe Zhong | 1 | -0/+41 |
| 2022-12-02 | RISC-V: Add duplicate vector support. | Ju-Zhe Zhong | 1 | -17/+69 |
| 2022-11-11 | RISC-V: Add RVV registers register spilling | Ju-Zhe Zhong | 1 | -31/+16 |
| 2022-10-26 | RISC-V: Support load/store in mov<mode> pattern for RVV modes. | Ju-Zhe Zhong | 1 | -0/+180 |
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index : riscv-gnu-toolchain/gcc.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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