riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-12-02	RISC-V: Add duplicate vector support.	Ju-Zhe Zhong	1	-0/+5
2022-10-27	RISC-V: Limit regs use for z*inx extension.	Jiawei	1	-2/+3
2022-10-26	RISC-V: Support load/store in mov<mode> pattern for RVV modes.	Ju-Zhe Zhong	1	-0/+22
2022-09-01	RISC-V: Add RVV constraints.	zhongjuzhe	1	-0/+20
2022-08-24	[RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand	Andrew Pinski	1	-0/+10
2022-08-24	[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask	Andrew Pinski	1	-0/+12
2022-08-24	[RISCV] Use constraints/predicates instead of checking const_int directly for...	Andrew Pinski	1	-0/+6
2022-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2021-07-13	docs: Add 'S' to Machine Constraints for RISC-V	Kito Cheng	1	-2/+1
2021-01-04	Update copyright years.	Jakub Jelinek	1	-1/+1
2020-01-01	Update copyright years.	Jakub Jelinek	1	-1/+1
2019-04-30	RISC-V: Short-forward-branch opt for SiFive 7 series cores.	Andrew Waterman	1	-0/+5
2019-01-01	Update copyright years.	Jakub Jelinek	1	-1/+1
2018-01-03	Update copyright years.	Jakub Jelinek	1	-1/+1
2017-02-06	RISC-V Port: gcc	Palmer Dabbelt	1	-0/+78