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| author | Jiawei <jiawei@iscas.ac.cn> | 2022-10-20 17:32:34 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-27 11:17:32 +0800 |
| commit | 6b252dc96b52f5ab6f399c3f6b0c0b6614a36913 (patch) | |
| tree | e043c93c86e95f1dd20588ef8838e6269cb427f1 /gcc/config/riscv/constraints.md | |
| parent | ac96e9068ce7dcaca992fde7f1551ffe8837b723 (diff) | |
| download | gcc-6b252dc96b52f5ab6f399c3f6b0c0b6614a36913.zip gcc-6b252dc96b52f5ab6f399c3f6b0c0b6614a36913.tar.gz gcc-6b252dc96b52f5ab6f399c3f6b0c0b6614a36913.tar.bz2 | |
RISC-V: Limit regs use for z*inx extension.
Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.
Co-Authored-By: Sinan Lin <sinan@isrc.iscas.ac.cn>
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
use while Zfinx is enable.
* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
registers use when Zdinx enable in RV32 cases.
(riscv_option_override): New target enable MASK_FDIV.
(riscv_libgcc_floating_mode_supported_p): New error info when
use incompatible arch&abi.
(riscv_excess_precision): New target enable FLOAT16.
Diffstat (limited to 'gcc/config/riscv/constraints.md')
| -rw-r--r-- | gcc/config/riscv/constraints.md | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 951dcc5..4088c48 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -21,8 +21,9 @@ ;; Register constraints -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" - "A floating-point register (if available).") +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : + (TARGET_ZFINX ? GR_REGS : NO_REGS)" + "A floating-point register (if available, reuse GPR as FPR when use zfinx).") (define_register_constraint "j" "SIBCALL_REGS" "@internal") |