| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-09-02 | i386: Optimize generate insn for AVX10.2 compare | Hu, Lin1 | 1 | -0/+12 |
| 2024-08-02 | i386: Fix comment/naming for APX NDD constraints | Lingling Kong | 1 | -10/+12 |
| 2024-07-18 | Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOV | liuhongt | 1 | -0/+5 |
| 2024-07-15 | AVX512BF16: Do not allow permutation with vcvtne2ps2bf16 [PR115889] | Hongyu Wang | 1 | -11/+0 |
| 2024-06-18 | i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx | Hu, Lin1 | 1 | -0/+5 |
| 2024-06-17 | x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevector | Levy Hsu | 1 | -0/+11 |
| 2024-06-07 | i386: Improve handling of ternlog instructions in i386/sse.md | Roger Sayle | 1 | -0/+5 |
| 2024-02-24 | Use HOST_WIDE_INT_{C,UC,0,0U,1,1U} macros some more | Jakub Jelinek | 1 | -2/+2 |
| 2024-02-23 | x86-64: Check R_X86_64_CODE_6_GOTTPOFF support | H.J. Lu | 1 | -1/+5 |
| 2024-02-08 | x86: Update constraints for APX NDD instructions | H.J. Lu | 1 | -0/+65 |
| 2024-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2023-11-07 | i386: Make flags_reg_operand a special predicate | Uros Bizjak | 1 | -1/+1 |
| 2023-11-06 | i386: Use "addr" attribute to limit address regclass to non-REX regs | Uros Bizjak | 1 | -18/+0 |
| 2023-10-24 | i386: Fix unprotected REGNO in aeswidekl_operation | Richard Sandiford | 1 | -0/+1 |
| 2023-10-09 | Support -mevex512 for AVX512F intrins | Haochen Jiang | 1 | -1/+2 |
| 2023-07-12 | Break false dependence for vpternlog by inserting vpxor or setting constraint... | liuhongt | 1 | -1/+7 |
| 2023-06-28 | i386: Add cbranchti4 pattern to i386.md (for -m32 compare_by_pieces). | Roger Sayle | 1 | -0/+12 |
| 2023-05-05 | i386: Rename index_register_operand predicate to register_no_SP_operand | Uros Bizjak | 1 | -2/+2 |
| 2023-05-04 | i386: Tighten ashift to lea splitter operand predicates [PR109733] | Uros Bizjak | 1 | -0/+5 |
| 2023-05-04 | i386: Improve index_register_operand predicate | Uros Bizjak | 1 | -24/+21 |
| 2023-04-21 | i386: Remove REG_OK_FOR_INDEX/REG_OK_FOR_BASE and their derivatives | Uros Bizjak | 1 | -2/+3 |
| 2023-04-20 | arch: Use VIRTUAL_REGISTER_P predicate. | Uros Bizjak | 1 | -3/+2 |
| 2023-04-20 | i386: Handle sign-extract for QImode operations with high registers [PR78952] | Uros Bizjak | 1 | -0/+3 |
| 2023-02-20 | i386: Introduce general_x64constmem_operand predicate | Uros Bizjak | 1 | -0/+7 |
| 2023-02-17 | ii386: Generate QImode binary ops with high-part input register [PR108831] | Uros Bizjak | 1 | -0/+7 |
| 2023-02-15 | i386: Rename extr_register_operand to int248_register_operand | Uros Bizjak | 1 | -2/+2 |
| 2023-02-13 | i386: Relax extract location operand mode requirements [PR108516] | Uros Bizjak | 1 | -0/+8 |
| 2023-01-16 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2022-11-08 | i386: Improve vector [GL]E{,U} comparison against vector constants [PR107546] | Jakub Jelinek | 1 | -0/+7 |
| 2022-11-07 | Support Intel prefetchit0/t1 | Haochen Jiang | 1 | -0/+15 |
| 2022-09-28 | i386: Mark XMM4-XMM6 as clobbered by encodekey128/encodekey256 | H.J. Lu | 1 | -10/+10 |
| 2022-09-23 | i386: Optimize code generation of __mm256_zextsi128_si256(__mm_set1_epi8(-1)) | Hu, Lin1 | 1 | -0/+49 |
| 2022-08-13 | Move V1TI shift/rotate lowering from expand to pre-reload split on x86_64. | Roger Sayle | 1 | -0/+8 |
| 2022-07-22 | Extend 16/32-bit vector bit_op patterns with (m,0,i) alternative. | liuhongt | 1 | -0/+4 |
| 2022-07-18 | Fix issue with x86_64_const_vector_operand predicate on x86. | Roger Sayle | 1 | -0/+4 |
| 2022-07-03 | x86: Support 2/4/8 byte constant vector stores | H.J. Lu | 1 | -0/+11 |
| 2022-06-13 | i386: Return true for (SUBREG (MEM....)) in register_no_elim_operand [PR105927] | Uros Bizjak | 1 | -0/+7 |
| 2022-05-10 | Avoid andb %dil when optimizing for size. | Roger Sayle | 1 | -0/+5 |
| 2022-01-23 | x86: Also check mode of memory broadcast in bcst_mem_operand | H.J. Lu | 1 | -0/+2 |
| 2022-01-03 | Update copyright years. | Jakub Jelinek | 1 | -1/+1 |
| 2021-12-15 | Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_o... | Haochen Jiang | 1 | -0/+13 |
| 2021-11-08 | Fix couple of issues in large PIC model on x86-64/VxWorks | Eric Botcazou | 1 | -2/+4 |
| 2021-11-04 | Extend vternlog define_insn_and_split to memory_operand to enable more optimz... | liuhongt | 1 | -3/+3 |
| 2021-08-24 | Optimize (a & b) | (c & ~b) to vpternlog instruction. | liuhongt | 1 | -0/+7 |
| 2021-08-16 | Optimize __builtin_shuffle_vector. | liuhongt | 1 | -0/+90 |
| 2021-08-10 | Support cond_ashr/lshr/ashl for vector integer modes under AVX512. | liuhongt | 1 | -0/+4 |
| 2021-07-12 | i386: Fix vec_set<mode> expanders [PR101424] | Uros Bizjak | 1 | -1/+6 |
| 2021-07-06 | i386: Add variable vec_set for 32bit vectors [PR97194] | Uros Bizjak | 1 | -1/+1 |
| 2021-07-01 | i386: Return true/false instead of 1/0 from predicates. | Uros Bizjak | 1 | -7/+7 |
| 2021-06-17 | i386: Add variable vec_set for 64bit vectors [PR97194] | Uros Bizjak | 1 | -0/+6 |
