aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/i386/i386.md
AgeCommit message (Expand)AuthorFilesLines
11 daysx86: Implement Fast-Math Float Truncation to BF16 via PSRLD InstructionLevy Hsu1-7/+9
13 daysssa-math-opts, i386: Improve spaceship expansion [PR116896]Jakub Jelinek1-6/+70
2024-09-19i386: Add ssemov2, sseicvt2 for some load instructions that use memory on ope...Hu, Lin11-4/+7
2024-09-12i386: Use offsetable address constraint for double-word memory operands, part 2Uros Bizjak1-1/+1
2024-09-09i386: Use offsetable address constraint for double-word memory operandsUros Bizjak1-3/+3
2024-09-02i386: Optimize generate insn for AVX10.2 compareHu, Lin11-2/+29
2024-08-26AVX10.2: Support compare instructionsZhang, Jun1-0/+1
2024-08-26AVX10.2: Support vector copy instructionsZhang, Jun1-1/+2
2024-08-15i386: Improve split of *extendv2di2_highpart_stv_noavx512vl.Roger Sayle1-2/+30
2024-08-15Movement between GENERAL_REGS and SSE_REGS for TImode doesn't need secondary ...liuhongt1-0/+19
2024-08-14i386: Optimization for APX NDD is always zero-uppered for shiftLingling Kong1-0/+66
2024-08-14i386: Optimization for APX NDD is always zero-uppered for logicLingling Kong1-0/+94
2024-08-14i386: Optimization for APX NDD is always zero-uppered for sub/adc/sbbLingling Kong1-8/+236
2024-08-14i386: Optimization for APX NDD is always zero-uppered for ADDLingling Kong1-0/+80
2024-08-12PR target/116275: Handle STV of *extenddi2_doubleword_highpart on i386.Roger Sayle1-0/+18
2024-08-02i386: Fix memory constraint for APX NFLingling Kong1-2/+3
2024-08-01Fix mismatch between constraint and predicate for ashl<mode>3_doubleword.liuhongt1-1/+1
2024-08-01i386: Remove ndd support for *add<mode>_4 [PR113744]Lingling Kong1-25/+15
2024-07-26i386: Use BLKmode for {ld,st}tilecfgHaochen Jiang1-7/+5
2024-07-23i386: Change prefetchi output templateHaochen Jiang1-1/+1
2024-07-15[APX NF] Add a pass to convert legacy insn to NF insnsHongyu Wang1-5/+62
2024-07-10i386: Swap compare operands in ustrunc patternsUros Bizjak1-3/+3
2024-07-09i386: Implement .SAT_TRUNC for unsigned integersUros Bizjak1-2/+110
2024-07-08i386: Promote {QI,HI}mode x86_mov<mode>cc_0_m1_neg to SImodeUros Bizjak1-6/+19
2024-07-04i386: Add additional variant of bswaphisi2_lowpart peephole2.Roger Sayle1-0/+24
2024-07-02i386: Support APX NF and NDD for imul/mulLingling Kong1-45/+53
2024-07-01i386: Additional peephole2 to use lea in round-up integer division.Roger Sayle1-0/+15
2024-07-01Extend lshifrtsi3_1_zext to ?k alternative.liuhongt1-6/+13
2024-06-28i386: Handle sign_extend like zero_extend in *concatditi3_[346]Roger Sayle1-3/+3
2024-06-13[APX CCMP] Use ctestcc when comparing to const 0Hongyu Wang1-4/+7
2024-06-13[APX ZU] Support APX zero-upperLingling Kong1-2/+23
2024-06-11i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV [PR112600]Uros Bizjak1-9/+53
2024-06-09i386: Implement .SAT_SUB for unsigned scalar integers [PR112600]Uros Bizjak1-1/+30
2024-06-08i386: Implement .SAT_ADD for unsigned scalar integers [PR112600]Uros Bizjak1-2/+22
2024-06-06[APX CCMP] Support APX CCMPHongyu Wang1-2/+33
2024-06-03i386: Force operand 1 of bswapsi2 to a register for !TARGET_BSWAP [PR115321]Uros Bizjak1-10/+11
2024-06-03[APX NF] Support APX NF for lzcnt/tzcnt/popcntLingling Kong1-11/+113
2024-06-03[APX NF] Support APX NF for mul/divLingling Kong1-17/+30
2024-06-03[APX NF] Support APX NF for shld/shrdLingling Kong1-81/+308
2024-06-03[APX NF] Support APX NF for rotate insnsLingling Kong1-21/+38
2024-06-03[APX NF] Support APX NF for right shift insnsLingling Kong1-36/+46
2024-06-03[APX NF] Support APX NF for left shift insnsLingling Kong1-26/+70
2024-06-03[APX NF] Support APX NF for {sub/and/or/xor/neg}Lingling Kong1-82/+91
2024-06-03[APX NF] Support APX NF addLingling Kong1-44/+93
2024-05-31i386: Rewrite bswaphi2 handling [PR115102]Uros Bizjak1-27/+50
2024-05-29Align tight&hot loop without considering max skipping bytes.liuhongt1-4/+6
2024-05-20i386: Remove Xeon Phi ISA supportHaochen Jiang1-16/+3
2024-04-28Adjust alternative *k to ?k for avx512 mask in zero_extend patternsliuhongt1-8/+8
2024-04-23i386: Avoid =&r,r,r andn double-word alternative for ia32 [PR114810]Jakub Jelinek1-4/+5
2024-04-15x86: Allow TImode offsettable memory only with 8-bit constantH.J. Lu1-17/+19