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AgeCommit message (Expand)AuthorFilesLines
2024-03-18Add AMD znver5 processor enablement with scheduler modelJan Hubicka1-1/+2
2024-03-16i386: Fix setup of incoming varargs for (...) functions which return large ag...Jakub Jelinek1-1/+2
2024-03-05i386: For noreturn functions save at least the bp register if it is used [PR1...Jakub Jelinek1-2/+8
2024-02-26i386: Enable _BitInt support on ia32Jakub Jelinek1-3/+1
2024-02-26i386: Fix up x86_function_profiler -masm=intel support [PR114094]Jakub Jelinek1-1/+1
2024-02-21ipa: Convert lattices from pure array to vector (PR 113476)Martin Jambor1-0/+2
2024-02-18x86-64: Generate push2/pop2 only if the incoming stack is 16-byte alignedH.J. Lu1-6/+18
2024-02-13x86-64: Use push2/pop2 only if the incoming stack is 16-byte alignedH.J. Lu1-0/+6
2024-02-08x86: Update constraints for APX NDD instructionsH.J. Lu1-25/+0
2024-02-06x86-64: Return 10_REG if there is no scratch registerH.J. Lu1-1/+1
2024-02-05x86-64: Find a scratch register for large model profilingH.J. Lu1-15/+76
2024-01-27x86: Add no_callee_saved_registers function attributeH.J. Lu1-13/+44
2024-01-18i386: Add -masm=intel profiling support [PR113122]Jakub Jelinek1-12/+51
2024-01-05asan: Align .LASANPC on function boundaryIlya Leoshkevich1-1/+1
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-28i386: Cleanup ix86_expand_{unary|binary}_operator issuesUros Bizjak1-17/+0
2023-12-20i386: Allow 64 bit mask register for -mno-evex512Haochen Jiang1-2/+1
2023-12-15bitint: Introduce abi_limb_modeJakub Jelinek1-0/+1
2023-12-13i386: Fix ICE on __builtin_ia32_pabsd128 without lhs [PR112962]Jakub Jelinek1-2/+8
2023-12-12Don't assume it's AVX_U128_CLEAN after call_insn whose abi.mode_clobber(V4DIm...liuhongt1-3/+19
2023-12-07[APX NDD] Support APX NDD for neg insnKong Lingling1-2/+3
2023-12-07[APX NDD] Disable seg_prefixed memory usage for NDD addHongyu Wang1-0/+25
2023-12-05Allow targets to add USEs to asmsRichard Sandiford1-2/+3
2023-12-05Take register pressure into account for vec_construct/scalar_to_vec when the ...liuhongt1-4/+50
2023-12-04i386: Fix rtl checking ICE in ix86_elim_entry_set_got [PR112837]Jakub Jelinek1-4/+5
2023-12-02Allow target attributes in non-gnu namespacesRichard Sandiford1-0/+5
2023-11-24i386: Fix ICE with -fsplit-stack -mcmodel=large [PR112686]Uros Bizjak1-4/+5
2023-11-23i386: Fix ICE with -mforce-indirect-call and -fsplit-stack [PR89316]Uros Bizjak1-25/+58
2023-11-21[APX PPX] Support Intel APX PPXHongyu Wang1-28/+42
2023-11-13i386: Rewrite pushfl<mode>2 and popfl<mode>1 as unspecsUros Bizjak1-0/+31
2023-11-13i386: Return CCmode from ix86_cc_mode for unknown RTX code [PR112494]Uros Bizjak1-5/+2
2023-11-11mode-switching: Pass the set of live registers to the after hookRichard Sandiford1-1/+1
2023-11-11mode-switching: Pass set of live registers to the needed hookRichard Sandiford1-1/+1
2023-11-09i386 PIE: accept @GOTOFF in load/store multi base addressAlexandre Oliva1-14/+75
2023-11-06i386: Use "addr" attribute to limit address regclass to non-REX regsUros Bizjak1-36/+35
2023-11-03i386: Handle multiple address register classesUros Bizjak1-44/+67
2023-10-27Support vec_cmpmn/vcondmn for v2hf/v4hf.liuhongt1-1/+5
2023-10-23i386: Prevent splitting to xmm16+ when !TARGET_AVX512VLHaochen Jiang1-0/+3
2023-10-22target: Support heap-based trampolinesAndrew Burgess1-1/+1
2023-10-16i386: Allow -mlarge-data-threshold with -mcmodel=largeUros Bizjak1-3/+6
2023-10-12[APX] Support Intel APX PUSH2POP2Mo, Zewei1-15/+237
2023-10-09Support -mevex512 for AVX512BW intrinsHaochen Jiang1-2/+2
2023-10-09Support -mevex512 for AVX512DQ intrinsHaochen Jiang1-6/+16
2023-10-09Support -mevex512 for AVX512F intrinsHaochen Jiang1-36/+65
2023-10-09Disable zmm register and 512 bit libmvec call when !TARGET_EVEX512Haochen Jiang1-24/+29
2023-10-08Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF.liuhongt1-0/+4
2023-10-07[APX EGPR] Handle legacy insns that only support GPR16 (3/5)Kong Lingling1-0/+13
2023-10-07[APX EGPR] Handle GPR16 only vector move insnsHongyu Wang1-6/+36
2023-10-07[APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint.Kong Lingling1-0/+92
2023-10-07[APX EGPR] Add backend hook for base_reg_class/index_reg_class.Kong Lingling1-0/+89
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