i386: Use "addr" attribute to limit address regclass to non-REX regs

Use "addr" attribute with "gpr8" value to limit address register class
to non-REX registers in instructions with high registers, where REX
registers can not be used in the address.

gcc/ChangeLog:

	* config/i386/constraints.md (Bc): Remove constraint.
	(Bn): Rewrite to use x86_extended_reg_mentioned_p predicate.
	* config/i386/i386.cc (ix86_memory_address_reg_class):
	Do not limit processing to TARGET_APX_EGPR.  Exit early for
	NULL insn.  Do not check recog_data.insn before calling
	extract_insn_cached.
	(ix86_insn_base_reg_class): Handle ADDR_GPR8.
	(ix86_regno_ok_for_insn_base_p): Ditto.
	(ix86_insn_index_reg_class): Ditto.
	* config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64):
	Remove insn pattern and corresponding peephole2 pattern.
	(*cmpi_ext<mode>_1): Remove (m,Q) alternative.
	Change (QBc,Q) alternative to (QBn,Q).  Add "addr" attribute.
	(*cmpqi_ext<mode>_3_mem_rex64): Remove insn pattern
	and corresponding peephole2 pattern.
	(*cmpi_ext<mode>_3): Remove (Q,m) alternative.
	Change (Q,QnBc) alternative to (Q,QnBn).  Add "addr" attribute.
	(*extzvqi_mem_rex64): Remove insn pattern and
	corresponding peephole2 pattern.
	(*extzvqi): Remove (Q,m) alternative.  Change (Q,QnBc)
	alternative to (Q,QnBn).  Add "addr" attribute.
	(*insvqi_1_mem_rex64): Remove insn pattern and
	corresponding peephole2 pattern.
	(*insvqi_1): Remove (Q,m) alternative.  Change (Q,QnBc)
	alternative to (Q,QnBn).  Add "addr" attribute.
	(@insv<mode>_1): Ditto.
	(*addqi_ext<mode>_0): Remove (m,0,Q) alternative.  Change (QBc,0,Q)
	alternative to (QBn,0,Q).  Add "addr" attribute.
	(*subqi_ext<mode>_0): Ditto.
	(*andqi_ext<mode>_0): Ditto.
	(*<any_or:code>qi_ext<mode>_0): Ditto.
	(*addqi_ext<mode>_1): Remove (Q,0,m) alternative.  Change (Q,0,QnBc)
	alternative to (Q,0,QnBn).  Add "addr" attribute.
	(*andqi_ext<mode>_1): Ditto.
	(*andqi_ext<mode>_1_cc): Ditto.
	(*<any_or:code>qi_ext<mode>_1): Ditto.
	(*xorqi_ext<mode>_1_cc): Ditto.
	* config/i386/predicates.md (nonimm_x64constmem_operand):
	Remove predicate.
	(general_x64constmem_operand): Ditto.
	(norex_memory_operand): Ditto.

1 files changed, 35 insertions, 36 deletions

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index fdc9362..c2bd07f 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -11366,50 +11366,49 @@ ix86_memory_address_reg_class (rtx_insn* insn)
      return maximum register class in this case.  */
   enum attr_addr addr_rclass = ADDR_GPR32;
 
-  if (TARGET_APX_EGPR && insn)
-    {
-      if (asm_noperands (PATTERN (insn)) >= 0
-	  || GET_CODE (PATTERN (insn)) == ASM_INPUT)
-	return ix86_apx_inline_asm_use_gpr32 ? ADDR_GPR32 : ADDR_GPR16;
+  if (!insn)
+    return addr_rclass;
 
-      /* Return maximum register class for unrecognized instructions.  */
-      if (INSN_CODE (insn) < 0)
-	return addr_rclass;
+  if (asm_noperands (PATTERN (insn)) >= 0
+      || GET_CODE (PATTERN (insn)) == ASM_INPUT)
+    return ix86_apx_inline_asm_use_gpr32 ? ADDR_GPR32 : ADDR_GPR16;
 
-      /* Try to recognize the insn before calling get_attr_addr.
-	 Save current recog_data and current alternative.  */
-      struct recog_data_d saved_recog_data = recog_data;
-      int saved_alternative = which_alternative;
+  /* Return maximum register class for unrecognized instructions.  */
+  if (INSN_CODE (insn) < 0)
+    return addr_rclass;
 
-      /* Update recog_data for processing of alternatives.  */
-      if (recog_data.insn != insn)
-	extract_insn_cached (insn);
+  /* Try to recognize the insn before calling get_attr_addr.
+     Save current recog_data and current alternative.  */
+  struct recog_data_d saved_recog_data = recog_data;
+  int saved_alternative = which_alternative;
 
-      /* If current alternative is not set, loop throught enabled
-	 alternatives and get the most limited register class.  */
-      if (saved_alternative == -1)
-	{
-	  alternative_mask enabled = get_enabled_alternatives (insn);
+  /* Update recog_data for processing of alternatives.  */
+  extract_insn_cached (insn);
 
-	  for (int i = 0; i < recog_data.n_alternatives; i++)
-	    {
-	      if (!TEST_BIT (enabled, i))
-		continue;
+  /* If current alternative is not set, loop throught enabled
+     alternatives and get the most limited register class.  */
+  if (saved_alternative == -1)
+    {
+      alternative_mask enabled = get_enabled_alternatives (insn);
 
-	      which_alternative = i;
-	      addr_rclass = MIN (addr_rclass, get_attr_addr (insn));
-	    }
-	}
-      else
+      for (int i = 0; i < recog_data.n_alternatives; i++)
 	{
-	  which_alternative = saved_alternative;
-	  addr_rclass = get_attr_addr (insn);
-	}
+	  if (!TEST_BIT (enabled, i))
+	    continue;
 
-      recog_data = saved_recog_data;
+	  which_alternative = i;
+	  addr_rclass = MIN (addr_rclass, get_attr_addr (insn));
+	}
+    }
+  else
+    {
       which_alternative = saved_alternative;
+      addr_rclass = get_attr_addr (insn);
     }
 
+  recog_data = saved_recog_data;
+  which_alternative = saved_alternative;
+
   return addr_rclass;
 }
 
@@ -11421,7 +11420,7 @@ ix86_insn_base_reg_class (rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_GENERAL_REGS;
     case ADDR_GPR16:
       return GENERAL_GPR16;
     case ADDR_GPR32:
@@ -11439,7 +11438,7 @@ ix86_regno_ok_for_insn_base_p (int regno, rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_INT_REGNO_P (regno);
     case ADDR_GPR16:
       return GENERAL_GPR16_REGNO_P (regno);
     case ADDR_GPR32:
@@ -11457,7 +11456,7 @@ ix86_insn_index_reg_class (rtx_insn* insn)
   switch (ix86_memory_address_reg_class (insn))
     {
     case ADDR_GPR8:
-      gcc_unreachable ();
+      return LEGACY_INDEX_REGS;
     case ADDR_GPR16:
       return INDEX_GPR16;
     case ADDR_GPR32: