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2024-01-12arm: vld1_types_x4 ACLE intrinsicsEzra Sitorus1-14/+142
2024-01-12arm: vld1_types_x3 ACLE intrinsicsEzra Sitorus1-14/+142
2024-01-12arm: vld1_types_x2 ACLE intrinsicsEzra Sitorus1-14/+142
2024-01-12arm: vst1q_types_x4 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vst1q_types_x3 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vst1q_types_x2 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vst1_types_x4 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vst1_types_x3 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vst1_types_x2 ACLE intrinsicsEzra Sitorus1-0/+114
2024-01-12arm: vld1q_types_x4 ACLE intrinsicsEzra Sitorus1-0/+128
2024-01-12arm: vld1q_types_x3 ACLE intrinsicsEzra Sitorus1-0/+128
2024-01-12arm: vld1q_types_x2 ACLE intrinsicsEzra Sitorus1-0/+128
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-08Revert "arm: vld1q_types_x2 ACLE intrinsics"Richard Earnshaw1-128/+0
2023-12-08Revert "arm: vld1q_types_x3 ACLE intrinsics"Richard Earnshaw1-128/+0
2023-12-08Revert "arm: vld1q_types_x4 ACLE intrinsics"Richard Earnshaw1-128/+0
2023-12-08Revert "arm: vst1_types_x2 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vst1_types_x3 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vst1_types_x4 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vst1q_types_x2 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vst1q_types_x3 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vst1q_types_x4 ACLE intrinsics"Richard Earnshaw1-114/+0
2023-12-08Revert "arm: vld1_types_x2 ACLE intrinsics"Richard Earnshaw1-142/+14
2023-12-08Revert "arm: vld1_types_x3 ACLE intrinsics"Richard Earnshaw1-142/+14
2023-12-08Revert "arm: vld1_types_x4 ACLE intrinsics"Richard Earnshaw1-142/+14
2023-12-07arm: vld1_types_x4 ACLE intrinsicsEzra Sitorus1-14/+142
2023-12-07arm: vld1_types_x3 ACLE intrinsicsEzra Sitorus1-14/+142
2023-12-07arm: vld1_types_x2 ACLE intrinsicsEzra Sitorus1-14/+142
2023-12-07arm: vst1q_types_x4 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vst1q_types_x3 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vst1q_types_x2 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vst1_types_x4 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vst1_types_x3 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vst1_types_x2 ACLE intrinsicsEzra Sitorus1-0/+114
2023-12-07arm: vld1q_types_x4 ACLE intrinsicsEzra Sitorus1-0/+128
2023-12-07arm: vld1q_types_x3 ACLE intrinsicsEzra Sitorus1-0/+128
2023-12-07arm: vld1q_types_x2 ACLE intrinsicsEzra Sitorus1-0/+128
2023-01-02Update copyright years.Jakub Jelinek1-1/+1
2022-02-07AArch32: correct usdot-product RTL patterns.Tamar Christina1-0/+39
2022-02-07AArch32: correct dot-product RTL patterns.Tamar Christina1-0/+29
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-08-11arm/66791: Replace builtins for vdup_n and vmov_n intrinsics.prathamesh.kulkarni1-52/+55
2021-07-30arm/66791: Replace builtins in vld1.prathamesh.kulkarni1-3/+3
2021-07-12arm/66791: Replace builtins for unsigned and fp vmul_n intrinsics.prathamesh.kulkarni1-4/+20
2021-06-30arm/66791: Gate comparison in vca intrinsics on __FAST_MATH__.prathamesh.kulkarni1-98/+161
2021-06-21arm/66791: Replace builtins in vceq_* (a, b) with a == b.prathamesh.kulkarni1-14/+30
2021-05-14arm/PR66791: Replace calls to vtst builtin with it's boolean logic equivalent.prathamesh.kulkarni1-16/+16
2021-01-15arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsicsChristophe Lyon1-0/+31
2021-01-15Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics"Christophe Lyon1-31/+0
2021-01-15arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsicsChristophe Lyon1-0/+31
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