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2023-12-04RISC-V: Update crypto vector ISA info with latest specFeng Wang1-2/+4
This patch add the Zvkb subset of crypto vector extension. The corresponding test cases have aslo been modified. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zvkb ISA info. * config/riscv/riscv.opt: Add Mask(ZVKB) gcc/testsuite/ChangeLog: * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb. * gcc.target/riscv/zvkn.c: Ditto. * gcc.target/riscv/zvknc-1.c:Ditto. * gcc.target/riscv/zvknc-2.c:Ditto. * gcc.target/riscv/zvknc.c: Ditto. * gcc.target/riscv/zvkng-1.c:Ditto. * gcc.target/riscv/zvkng-2.c:Ditto. * gcc.target/riscv/zvkng.c: Ditto. * gcc.target/riscv/zvks-1.c: Ditto. * gcc.target/riscv/zvks.c: Ditto. * gcc.target/riscv/zvksc-1.c:Ditto. * gcc.target/riscv/zvksc-2.c:Ditto. * gcc.target/riscv/zvksc.c: Ditto. * gcc.target/riscv/zvksg-1.c:Ditto. * gcc.target/riscv/zvksg-2.c:Ditto. * gcc.target/riscv/zvksg.c: Ditto.
2023-12-04RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional ↵Kito Cheng1-11/+33
implication [NFC] RISC-V ISA implication rules become little bit complicated than before, it may come with condition, so this commit extend the capability of riscv_implied_info_t, also make it more...C++ize. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New. (riscv_implied_info_t::riscv_implied_info_t): New. (riscv_implied_info_t::match): New. (riscv_implied_info): New entry for zcf. (riscv_subset_list::handle_implied_ext): Use riscv_implied_info_t::match. (riscv_subset_list::check_implied_ext): Ditto. (riscv_subset_list::handle_combine_ext): Ditto. (riscv_subset_list::parse): Move zcf implication handling to riscv_implied_infos.
2023-12-04RISC-V: Refine riscv_subset_list::parse [NFC]Kito Cheng1-12/+19
Extract the logic of checking conflict extensions to a standard alone function, prepare to add more checking logic. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): New. (riscv_subset_list::parse): Move checking conflict ext. to check_conflict_ext. * config/riscv/riscv-subset.h: Add riscv_subset_list::check_conflict_ext.
2023-12-04i386: Fix CPUID of USER_MSR.Hu, Lin11-2/+2
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR to the correct location. gcc/testsuite/ChangeLog: * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user an proper example.
2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-4/+4
Along with RV32E, RV64E is ratified. Though ILP32E and LP64E ABIs are still draft, it's worth supporting it. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Set version to ratified 2.0. (riscv_subset_list::parse_std_ext): Allow RV64E. * config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'. * config/riscv/arch-canonicalize: Parse base ISA 'rv64e'. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define different macro per XLEN. Add handling for ABI_LP64E. * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi): Add handling for ABI_LP64E. * config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E. * config/riscv/riscv.cc (riscv_option_override): Enhance error handling to support RV64E and LP64E. (riscv_conditional_register_usage): Change "RV32E" in a comment to "RV32E/RV64E". * config/riscv/riscv.h (UNITS_PER_FP_ARG): Add handling for ABI_LP64E. (STACK_BOUNDARY): Ditto. (ABI_STACK_BOUNDARY): Ditto. (MAX_ARGS_IN_REGISTERS): Ditto. (ABI_SPEC): Add support for "lp64e". * config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E. * doc/invoke.texi: Add documentation of the LP64E ABI. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-1.c: Test for __riscv_64e. * gcc.target/riscv/predef-2.c: Ditto. * gcc.target/riscv/predef-3.c: Ditto. * gcc.target/riscv/predef-4.c: Ditto. * gcc.target/riscv/predef-5.c: Ditto. * gcc.target/riscv/predef-6.c: Ditto. * gcc.target/riscv/predef-7.c: Ditto. * gcc.target/riscv/predef-8.c: Ditto. * gcc.target/riscv/predef-9.c: New test for RV64E and LP64E, based on predef-7.c.
2023-11-20Initial support for AVX10.1Haochen Jiang4-1/+92
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_256_SET): New. (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1. (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512. Add indicator for explicit no-avx512 and no-avx10.1 options. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_1_256 and AVX10_1_512. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (check_avx10_avx512_features): New. (host_detect_local_cpu): Do not append "-mno-" options under specific scenarios to avoid emitting a warning. * config/i386/i386-isa.def (EVEX512): Add DEF_PTA(EVEX512). (AVX10_1_256): Add DEF_PTA(AVX10_1_256). (AVX10_1_512): Add DEF_PTA(AVX10_1_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and -mavx10.1-512. (ix86_function_specific_save): Save explicit no indicator. (ix86_function_specific_restore): Restore explicit no indicator. (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and avx10.1-512. (ix86_valid_target_attribute_tree): Handle avx512 function attributes with avx10.1 command line option. (ix86_option_override_internal): Handle AVX10.1 options. * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target machines. * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: New test. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto.
2023-11-15RISC-V: Fix ICE in non-canonical march parsingPatrick O'Neill1-4/+13
Passing in a base extension in non-canonical order (i, e, g) causes GCC to ICE: xgcc: error: '-march=rv64ge': ISA string is not in canonical order. 'e' xgcc: internal compiler error: in add, at common/config/riscv/riscv-common.cc:671 ... This is fixed by skipping to the next extension when a non-canonical order is detected. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_std_ext): Emit an error and skip to the next extension when a non-canonical ordering is detected. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-27.c: New test. * gcc.target/riscv/arch-28.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-10-30i386: Zhaoxin yongfeng enablementMayshao3-5/+12
Enable -march/-mtune=yongfeng. Costs and tunings are set according to the characteristics of the processor. Add a new .md file to describe yongfeng processor. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize yongfeng. * common/config/i386/i386-common.cc: Add yongfeng. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add ZHAOXIN_FAM7H_YONGFENG. * config.gcc: Add yongfeng. * config/i386/driver-i386.cc (host_detect_local_cpu): Let -march=native recognize yongfeng processors. * config/i386/i386-c.cc (ix86_target_macros_internal): Add yongfeng. * config/i386/i386-options.cc (m_YONGFENG): New definition. (m_ZHAOXIN): Ditto. * config/i386/i386.h (enum processor_type): Add PROCESSOR_YONGFENG. * config/i386/i386.md: Add yongfeng. * config/i386/lujiazui.md: Fix typo. * config/i386/x86-tune-costs.h (struct processor_costs): Add yongfeng costs. * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add yongfeng. (ix86_adjust_cost): Ditto. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Replace m_LUJIAZUI with m_ZHAOXIN. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_MOVX): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto. (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto. (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto. (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_LCP_STALL): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_OPT_AGU): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_EXPAND_ABS): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_USE_FFREEP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. (X86_TUNE_USE_GATHER_2PARTS): Add m_YONGFENG. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER_8PARTS): Ditto. (X86_TUNE_AVOID_128FMA_CHAINS): Ditto. * doc/extend.texi: Add details about yongfeng. * doc/invoke.texi: Ditto. * config/i386/yongfeng.md: New file to describe yongfeng processor. gcc/testsuite/ChangeLog: * g++.target/i386/mv32.C: Handle new -march. * gcc.target/i386/funcspec-56.inc: Ditto.
2023-10-22RISC-V: Prohibit combination of 'E' and 'H'Tsukasa OI1-0/+4
According to the ratified privileged specification (version 20211203), it says: > The hypervisor extension depends on an "I" base integer ISA with 32 x > registers (RV32I or RV64I), not RV32E, which has only 16 x registers. Also in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Prohibit 'E' and 'H' combinations. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-26.c: New test.
2023-10-22RISC-V: 'Zfa' extension is now ratifiedTsukasa OI1-1/+1
Since this extension is ratified, it now has the version number 1.0. Reference: <https://github.com/riscv/riscv-isa-manual/pull/1096> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Change version number of the 'Zfa' extension to 1.0.
2023-10-18Initial Panther Lake SupportHaochen Jiang3-0/+12
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Add Panther Lake. * common/config/i386/i386-common.cc (processor_name): Ditto. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_PANTHERLAKE. * config.gcc: Add -march=pantherlake. * config/i386/driver-i386.cc (host_detect_local_cpu): Refactor the if clause. Handle pantherlake. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle pantherlake. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_PANTHERLAKE): New. (m_CORE_HYBRID): Add pantherlake. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-10-18Initial Clearwater Forest SupportHaochen Jiang3-0/+10
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Clearwater Forest. * common/config/i386/i386-common.cc (processor_name): Add Clearwater Forest. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_CLEARWATERFOREST. * config.gcc: Add -march=clearwaterforest. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle clearwaterforest. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_CLEARWATERFOREST): New. (m_CORE_ATOM): Add clearwaterforest. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-10-12Support Intel USER_MSRHu, Lin14-0/+19
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect USER_MSR. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_USER_MSR_SET): New. (OPTION_MASK_ISA2_USER_MSR_UNSET): Ditto. (ix86_handle_option): Handle -musermsr. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_USER_MSR. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for usermsr. * config.gcc: Add usermsrintrin.h * config/i386/cpuid.h (bit_USER_MSR): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (VOID, UINT64, UINT64). * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Add __builtin_urdmsr and __builtin_uwrmsr. * config/i386/i386-builtins.h (ix86_builtins): Add IX86_BUILTIN_URDMSR and IX86_BUILTIN_UWRMSR. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __USER_MSR__. * config/i386/i386-expand.cc (ix86_expand_builtin): Handle new builtins. * config/i386/i386-isa.def (USER_MSR): Add DEF_PTA(USER_MSR). * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle usermsr. * config/i386/i386.md (urdmsr): New define_insn. (uwrmsr): Ditto. * config/i386/i386.opt: Add option -musermsr. * config/i386/x86gprintrin.h: Include usermsrintrin.h * doc/extend.texi: Document usermsr. * doc/invoke.texi: Document -musermsr. * doc/sourcebuild.texi: Document target usermsr. * config/i386/usermsrintrin.h: New file. gcc/testsuite/ChangeLog: * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -musermsr for 64bit target. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add musermsr for 64bit target. * gcc.target/i386/x86gprintrin-5.c: Ditto * gcc.target/i386/user_msr-1.c: New test. * gcc.target/i386/user_msr-2.c: Ditto.
2023-10-11RISC-V: Extend riscv_subset_list, preparatory for target attribute supportKito Cheng1-0/+209
riscv_subset_list only accept a full arch string before, but we need to parse single extension when supporting target attribute, also we may set a riscv_subset_list directly rather than re-parsing the ISA string again. gcc/ChangeLog: * config/riscv/riscv-subset.h (riscv_subset_list::parse_single_std_ext): New. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::clone): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::set_loc): Ditto. (riscv_set_arch_by_subset_list): Ditto. * common/config/riscv/riscv-common.cc (riscv_subset_list::parse_single_std_ext): New. (riscv_subset_list::parse_single_multiletter_ext): Ditto. (riscv_subset_list::clone): Ditto. (riscv_subset_list::parse_single_ext): Ditto. (riscv_subset_list::set_loc): Ditto. (riscv_set_arch_by_subset_list): Ditto.
2023-10-11[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+2
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add the XCValu extension. * config/riscv/constraints.md: Add builtins for the XCValu extension. * config/riscv/predicates.md (immediate_register_operand): Likewise. * config/riscv/corev.def: Likewise. * config/riscv/corev.md: Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Likewise. (RISCV_ATYPE_UHI): Likewise. * config/riscv/riscv-ftypes.def: Likewise. * config/riscv/riscv.opt: Likewise. * config/riscv/riscv.cc (riscv_print_operand): Likewise. * doc/extend.texi: Add XCValu documentation. * doc/sourcebuild.texi: Likewise. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add proc for the XCValu extension. * gcc.target/riscv/cv-alu-compile.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addrn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addun.c: New test. * gcc.target/riscv/cv-alu-fail-compile-addurn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-clip.c: New test. * gcc.target/riscv/cv-alu-fail-compile-clipu.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subrn.c: New test. * gcc.target/riscv/cv-alu-fail-compile-subun.c: New test. * gcc.target/riscv/cv-alu-fail-compile-suburn.c: New test. * gcc.target/riscv/cv-alu-fail-compile.c: New test.
2023-10-11[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+4
Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add XCVmac. * config/riscv/riscv-ftypes.def: Add XCVmac builtins. * config/riscv/riscv-builtins.cc: Likewise. * config/riscv/riscv.md: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Add XCVmac builtin documentation. * doc/sourcebuild.texi: Likewise. * config/riscv/corev.def: New file. * config/riscv/corev.md: New file. gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add new effective target check. * gcc.target/riscv/cv-mac-compile.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mac.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-machhurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-macurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-msu.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulsn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulsrn.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulun.c: New test. * gcc.target/riscv/cv-mac-fail-compile-mulurn.c: New test. * gcc.target/riscv/cv-mac-test-autogeneration.c: New test.
2023-10-09Initial support for -mevex512Haochen Jiang1-0/+15
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_EVEX512_SET): New. (OPTION_MASK_ISA2_EVEX512_UNSET): Ditto. (ix86_handle_option): Handle EVEX512. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__ when AVX512VL is set. * config/i386/i386-options.cc: (isa2_opts): Handle EVEX512. (ix86_valid_target_attribute_inner_p): Ditto. (ix86_option_override_internal): Set EVEX512 target if it is not explicitly set when AVX512 is enabled. Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. * config/i386/i386.opt: Add mevex512. Temporaily RejectNegative.
2023-10-07[APX_EGPR] Initial support for APX_FKong Lingling4-1/+30
Add -mapx-features= enumeration to separate subfeatures of APX_F. -mapxf is treated same as previous ISA flag, while it sets -mapx-features=apx_all that enables all subfeatures. gcc/ChangeLog: * common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro. (XCR_APX_F_ENABLED_MASK): Likewise. (get_available_features): Detect APX_F under * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_APX_F_SET): New. (OPTION_MASK_ISA2_APX_F_UNSET): Likewise. (ix86_handle_option): Handle -mapxf. * common/config/i386/i386-cpuinfo.h (FEATURE_APX_F): New. * common/config/i386/i386-isas.h: Add entry for APX_F. * config/i386/cpuid.h (bit_APX_F): New. * config/i386/i386.h (bit_APX_F): (TARGET_APX_EGPR, TARGET_APX_PUSH2POP2, TARGET_APX_NDD): New define. * config/i386/i386-opts.h (enum apx_features): New enum. * config/i386/i386-isa.def (APX_F): New DEF_PTA. * config/i386/i386-options.cc (ix86_function_specific_save): Save ix86_apx_features. (ix86_function_specific_restore): Restore it. (ix86_valid_target_attribute_inner_p): Add mapxf. (ix86_option_override_internal): Set ix86_apx_features for PTA and TARGET_APX_F. Also reports error when APX_F is set but not having TARGET_64BIT. * config/i386/i386.opt: (-mapxf): New ISA flag option. (-mapx=): New enumeration option. (apx_features): New enum type. (apx_none): New enum value. (apx_egpr): Likewise. (apx_push2pop2): Likewise. (apx_ndd): Likewise. (apx_all): Likewise. * doc/invoke.texi: Document mapxf. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-1.c: New test. Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
2023-09-08LoongArch: Enable -fsched-pressure by default at -O1 and higher.Guo Jie1-0/+1
gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: (default_options loongarch_option_optimization_table): Default to -fsched-pressure.
2023-09-07RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' supportTsukasa OI1-0/+2
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems containing two instructions for conditional move and will be supported on their Veyron V1 CPU. And most notably (for historical reasons), 'XVentanaCondOps' and the standard 'Zicond' extension are functionally equivalent (only encodings and instruction names are different). * czero.eqz == vt.maskc * czero.nez == vt.maskcn This commit adds support for the 'XVentanaCondOps' extension by extending 'Zicond' extension support. With this, we can now reuse the optimization using the 'Zicond' extension for the 'XVentanaCondOps' extension. The specification for the 'XVentanaCondOps' extension is based on: <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Parse 'XVentanaCondOps' extension. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New. (TARGET_XVENTANACONDOPS): Ditto. (TARGET_ZICOND_LIKE): New to represent targets with conditional moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'. * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. (riscv_expand_conditional_move): Ditto. * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with TARGET_ZICOND_LIKE. * config/riscv/riscv.opt: Add new riscv_xventana_subext. * config/riscv/zicond.md: Modify description. (eqz_ventana): New to match corresponding czero instructions. (nez_ventana): Ditto. (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if 'Zicond' is not available but 'XVentanaCondOps' + RV64 is. (*czero.<eqz>.<GPR><X>): Ditto. (*czero.eqz.<GPR><X>.opt1): Ditto. (*czero.nez.<GPR><X>.opt2): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test, * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New test to make sure that XVentanaCondOps instructions are disabled on RV32. * gcc.target/riscv/xventanacondops-xor-01.c: New test,
2023-09-05arc: Remove obsolete mbbit-peephole option and unused patterns.Claudiu Zissulescu1-1/+0
gcc/ * common/config/arc/arc-common.cc (arc_option_optimization_table): Remove mbbit_peephole. * config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove. (store_direct): Likewise. (BBIT peephole2): Likewise. * config/arc/arc.opt (mbbit-peephole): Ignore option. * doc/invoke.texi (mbbit-peephole): Update document. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-08-29RISC-V: Add stub support for existing extensions (unprivileged)Tsukasa OI1-0/+1
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported standard unprivileged extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet merged 'Zce', 'Zcmp' and 'Zcmt' support). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from unprivileged extensions. (riscv_ext_version_table): Add stub support for all unprivileged extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-31.c: New test for a stub unprivileged extension 'Zcb' with some implications.
2023-08-29RISC-V: Add stub support for existing extensions (vendor)Tsukasa OI1-0/+2
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported vendor extensions to riscv_ext_version_table (no riscv_implied_info entries to add; all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add stub support for all vendor extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-30.c: New test for a stub vendor extension 'XVentanaCondOps'.
2023-08-29RISC-V: Add stub support for existing extensions (privileged)Tsukasa OI1-0/+18
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. As a start, this commit adds stub supported *privileged* extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from privileged extensions. (riscv_ext_version_table): Add stub support for all privileged extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-29.c: New test for a stub privileged extension 'Smstateen' with some implications.
2023-08-29LoongArch: Enable '-free' starting at -O2.Lulu Cheng1-0/+1
gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-free' on O2 and above. * doc/invoke.texi: Modify the description information of the '-free' compilation option and add the LoongArch description. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend.c: New test.
2023-08-28RISC-V: __builtin_riscv_pause for all environmentTsukasa OI1-0/+2
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension (in the assembler). However, GCC emits "pause" unconditionally, making an assembler error while compiling code with __builtin_riscv_pause while the 'Zihintpause' extension disabled. However, the "pause" instruction code (0x0100000f) is a HINT and emitting its instruction code is safe in any environment. This commit implements handling for the 'Zihintpause' extension and emits ".insn 0x0100000f" instead of "pause" only if the extension is disabled (making the diagnostics better). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Implement the 'Zihintpause' extension, version 2.0. (riscv_ext_flag_table) Add 'Zihintpause' handling. * config/riscv/riscv-builtins.cc: Remove availability predicate "always" and add "hint_pause". (riscv_builtins) : Add "pause" extension. * config/riscv/riscv-opts.h (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New. * config/riscv/riscv.md (riscv_pause): Adjust output based on TARGET_ZIHINTPAUSE. gcc/testsuite/ChangeLog: * gcc.target/riscv/builtin_pause.c: Removed. * gcc.target/riscv/zihintpause-1.c: New test when the 'Zihintpause' extension is enabled. * gcc.target/riscv/zihintpause-2.c: Likewise. * gcc.target/riscv/zihintpause-noarch.c: New test when the 'Zihintpause' extension is disabled.
2023-08-25[PATCH v10] RISC-V: Add support for the Zfa extensionJin Ma1-0/+7
This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2023-April/127060.html What needs special explanation is: 1, According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to accelerate the processing of JavaScript Numbers.", so it seems that no implementation is required. 2, The instructions FMINM and FMAXM correspond to C23 library function fminimum and fmaximum. Therefore, this patch has simply implemented the pattern of fminm<hf\sf\df>3 and fmaxm<hf\sf\df>3 to prepare for later. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zfa extension version, which depends on the F extension. * config/riscv/constraints.md (zfli): Constrain the floating point number that the instructions FLI.H/S/D can load. * config/riscv/iterators.md (ceil): New. * config/riscv/riscv-opts.h (MASK_ZFA): New. (TARGET_ZFA): New. * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): New. * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New. (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used, memory is not applicable. (riscv_const_insns): Likewise. (riscv_legitimize_const_move): Likewise. (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no split is required. (riscv_split_doubleword_move): Likewise. (riscv_output_move): Output the mov instructions in zfa extension. (riscv_print_operand): Output the floating-point value of the FLI.H/S/D immediate in assembly. (riscv_secondary_memory_needed): Likewise. * config/riscv/riscv.md (fminm<mode>3): New. (fmaxm<mode>3): New. (movsidf2_low_rv32): New. (movsidf2_high_rv32): New. (movdfsisi3_rv32): New. (f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_zfa): New. * config/riscv/riscv.opt: New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fleq-fltq.c: New test. * gcc.target/riscv/zfa-fli-zfh.c: New test. * gcc.target/riscv/zfa-fli.c: New test. * gcc.target/riscv/zfa-fmovh-fmovp.c: New test. * gcc.target/riscv/zfa-fli-1.c: New test. * gcc.target/riscv/zfa-fli-2.c: New test. * gcc.target/riscv/zfa-fli-3.c: New test. * gcc.target/riscv/zfa-fli-4.c: New test. * gcc.target/riscv/zfa-fli-6.c: New test. * gcc.target/riscv/zfa-fli-7.c: New test. * gcc.target/riscv/zfa-fli-8.c: New test. Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com>
2023-08-24RISC-V: Enable pressure-aware scheduling by default.Robin Dapp1-0/+2
this patch enables pressure-aware scheduling for riscv. There have been various requests for it so I figured I'd just go ahead and send the patch. There is some slight regression in code quality for a number of vector tests where we spill more due to different instructions order. The ones I looked at were a mix of bad luck and/or brittle tests. Comparing the size of the generated assembly or the number of vsetvls for SPECint also didn't show any immediate benefit but that's obviously not a very fine-grained analysis. As cost and scheduling models mature I expect the situation to improve and for now I think it's generally favorable to enable pressure-aware scheduling so we can work with it rather than trying to find every possible problem in advance. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add -fsched-pressure. * config/riscv/riscv.cc (riscv_option_override): Set sched pressure algorithm. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/narrow_constraint-1.c: Add -fno-sched-pressure. * gcc.target/riscv/rvv/base/narrow_constraint-17.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-18.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-19.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-20.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-21.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-22.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-23.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-24.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-25.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-26.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-27.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-28.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-29.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-30.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-31.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-4.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-5.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto. * gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto.
2023-08-24Revert "Initial support for AVX10.1"Haochen Jiang4-96/+1
This reverts commit 11ad44da01dd1c91c96e45802fd8b1c50e88703f.
2023-08-24Revert "Emit a warning when disabling AVX512 with AVX10 enabled or disabling ↵Haochen Jiang1-54/+14
AVX10 with AVX512 enabled" This reverts commit 0288ab14732a16b3787546cdd159941eb7306cf3.
2023-08-24Revert "Emit a warning when AVX10 options conflict in vector width"Haochen Jiang1-20/+0
This reverts commit 26a820dc136b00b4dc37609429576b6a914cb572.
2023-08-24Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")liuhongt1-4/+7
Both "graniterapid-d" and "graniterapids" are attached with PROCESSOR_GRANITERAPID in processor_alias_table but mapped to different __cpu_subtype in get_intel_cpu. And get_builtin_code_for_version will try to match the first PROCESSOR_GRANITERAPIDS in processor_alias_table which maps to "granitepraids" here. 861 else if (new_target->arch_specified && new_target->arch > 0) 1862 for (i = 0; i < pta_size; i++) 1863 if (processor_alias_table[i].processor == new_target->arch) 1864 { 1865 const pta *arch_info = &processor_alias_table[i]; 1866 switch (arch_info->priority) 1867 { 1868 default: 1869 arg_str = arch_info->name; This mismatch makes dispatch_function_versions check the preidcate of__builtin_cpu_is ("graniterapids") for "graniterapids-d" and causes the issue. The patch explicitly adds PROCESSOR_ARROWLAKE_S and PROCESSOR_GRANITERAPIDS_D to make a distinction. For "alderlake","raptorlake", "meteorlake" they share same isa, cost, tuning, and mapped to the same __cpu_type/__cpu_subtype in get_intel_cpu, so no need to add PROCESSOR_RAPTORLAKE and others. gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_names): Add new member graniterapids-s and arrowlake-s. * config/i386/i386-options.cc (processor_alias_table): Update table with PROCESSOR_ARROWLAKE_S and PROCESSOR_GRANITERAPIDS_D. (m_GRANITERAPID_D): New macro. (m_ARROWLAKE_S): Ditto. (m_CORE_AVX512): Add m_GRANITERAPIDS_D. (processor_cost_table): Add icelake_cost for PROCESSOR_GRANITERAPIDS_D and alderlake_cost for PROCESSOR_ARROWLAKE_S. * config/i386/x86-tune.def: Hanlde m_ARROWLAKE_S same as m_ARROWLAKE. * config/i386/i386.h (enum processor_type): Add new member PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle PROCESSOR_GRANITERAPIDS_D and PROCESSOR_ARROWLAKE_S
2023-08-21Support -march=gracemontliuhongt2-0/+5
Alderlake-N is E-core only, add it as an alias of Alderlake. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Alderlake-N. * common/config/i386/i386-common.cc (alias_table): Support -march=gracemont as an alias of -march=alderlake.
2023-08-17Emit a warning when AVX10 options conflict in vector widthHaochen Jiang1-0/+20
gcc/ChangeLog: * common/config/i386/i386-common.cc (ix86_check_avx10_vector_width): New function to check isa_flags to emit a warning when there is a conflict in AVX10 options for vector width. (ix86_handle_option): Add check for avx10.1-256 and avx10.1-512. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10-max-512bit for -march=native. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-15.c: New test. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto.
2023-08-17Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 ↵Haochen Jiang1-14/+54
with AVX512 enabled gcc/ChangeLog: * common/config/i386/i386-common.cc (ix86_check_avx10): New function to check isa_flags and isa_flags_explicit to emit warning when AVX10 is enabled by "-m" option. (ix86_check_avx512): New function to check isa_flags and isa_flags_explicit to emit warning when AVX512 is enabled by "-m" option. (ix86_handle_option): Do not change the flags when warning is emitted. * config/i386/driver-i386.cc (host_detect_local_cpu): Do not append -mno-avx10.1 for -march=native. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-11.c: New test. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto.
2023-08-17Initial support for AVX10.1Haochen Jiang4-1/+96
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_512BIT_SET): New. (OPTION_MASK_ISA2_AVX10_1_SET): Ditto. (OPTION_MASK_ISA2_AVX10_512BIT_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10_1. (ix86_handle_option): Handle -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_512BIT, FEATURE_AVX10_1 and FEATURE_AVX10_512BIT. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_512BIT, AVX10_1 and AVX10_1_512. * config/i386/constraints.md (Yk): Add AVX10_1. (Yv): Ditto. (k): Ditto. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/i386-c.cc (ix86_target_macros_internal): Define AVX10_512BIT and AVX10_1. * config/i386/i386-isa.def (AVX10_512BIT): Add DEF_PTA(AVX10_512BIT). (AVX10_1): Add DEF_PTA(AVX10_1). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1. (ix86_valid_target_attribute_inner_p): Handle avx10-512bit, avx10.1 and avx10.1-512. (ix86_option_override_internal): Enable AVX512{F,VL,BW,DQ,CD,BF16, FP16,VBMI,VBMI2,VNNI,IFMA,BITALG,VPOPCNTDQ} features for avx10.1-512. (ix86_valid_target_attribute_inner_p): Handle AVX10_1. * config/i386/i386.cc (ix86_get_ssemov): Add AVX10_1. (ix86_conditional_register_usage): Ditto. (ix86_hard_regno_mode_ok): Ditto. (ix86_rtx_costs): Ditto. * config/i386/i386.h (VALID_MASK_AVX10_MODE): New macro. * config/i386/i386.opt: Add option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * g++.target/i386/mv33.C: New test. * gcc.target/i386/avx10_1-1.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto. * gcc.target/i386/avx10_1-10.c: Ditto.
2023-08-14RISC-V: Minimal support for ZC* extensions.Jiawei1-0/+38
This patch is the minimal support for ZC* extensions, include the extension name, mask and target defination. Also define the dependencies with Zca and Zce extension. Notes that all ZC* extensions depend on the Zca extension. Zce includes all relevant ZC* extensions for microcontrollers using. Zce will imply zcf when 'f' extension enabled in rv32. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions. * config/riscv/riscv-opts.h (MASK_ZCA): New mask. (MASK_ZCB): Ditto. (MASK_ZCE): Ditto. (MASK_ZCF): Ditto. (MASK_ZCD): Ditto. (MASK_ZCMP): Ditto. (MASK_ZCMT): Ditto. (TARGET_ZCA): New target. (TARGET_ZCB): Ditto. (TARGET_ZCE): Ditto. (TARGET_ZCF): Ditto. (TARGET_ZCD): Ditto. (TARGET_ZCMP): Ditto. (TARGET_ZCMT): Ditto. * config/riscv/riscv.opt: New target variable.
2023-08-14x86: Update model values for Raptorlake.Cui, Lili1-0/+1
Update model values for Raptorlake according to SDM. gcc/ChangeLog * common/config/i386/cpuinfo.h (get_intel_cpu): Add model value 0xba to Raptorlake.
2023-08-10RISC-V: Add Ztso atomic mappingsPatrick O'Neill1-0/+6
The RISC-V Ztso extension currently has no effect on generated code. With the additional ordering constraints guarenteed by Ztso, we can emit more optimized atomic mappings than the RVWMO mappings. This PR implements the Ztso psABI mappings[1]. [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/391 2023-08-08 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Ztso and mark Ztso as dependent on 'a' extension. * config/riscv/riscv-opts.h (MASK_ZTSO): New mask. (TARGET_ZTSO): New target. * config/riscv/riscv.cc (riscv_memmodel_needs_amo_acquire): Add Ztso case. (riscv_memmodel_needs_amo_release): Add Ztso case. (riscv_print_operand): Add Ztso case for LR/SC annotations. * config/riscv/riscv.md: Import sync-rvwmo.md and sync-ztso.md. * config/riscv/riscv.opt: Add Ztso target variable. * config/riscv/sync.md (mem_thread_fence_1): Expand to RVWMO or Ztso specific insn. (atomic_load<mode>): Expand to RVWMO or Ztso specific insn. (atomic_store<mode>): Expand to RVWMO or Ztso specific insn. * config/riscv/sync-rvwmo.md: New file. Seperate out RVWMO specific load/store/fence mappings. * config/riscv/sync-ztso.md: New file. Seperate out Ztso specific load/store/fence mappings. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-ztso-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-amo-add-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-ztso-fence-1.c: New test. * gcc.target/riscv/amo-table-ztso-fence-2.c: New test. * gcc.target/riscv/amo-table-ztso-fence-3.c: New test. * gcc.target/riscv/amo-table-ztso-fence-4.c: New test. * gcc.target/riscv/amo-table-ztso-fence-5.c: New test. * gcc.target/riscv/amo-table-ztso-load-1.c: New test. * gcc.target/riscv/amo-table-ztso-load-2.c: New test. * gcc.target/riscv/amo-table-ztso-load-3.c: New test. * gcc.target/riscv/amo-table-ztso-store-1.c: New test. * gcc.target/riscv/amo-table-ztso-store-2.c: New test. * gcc.target/riscv/amo-table-ztso-store-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-08-09RISC-V: Remove non-existing 'Zve32d' extensionTsukasa OI1-1/+0
Since this extension does not exist, this commit prunes this from the defined extension version table. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Remove 'Zve32d' from the version list.
2023-08-09Rename local variable subleaf_level to max_subleaf_level.liuhongt1-3/+4
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Rename local variable subleaf_level to max_subleaf_level.
2023-08-09Workaround possible CPUID bug in Sandy Bridge.liuhongt1-39/+43
Don't access leaf 7 subleaf 1 unless subleaf 0 says it is supported via EAX. Intel documentation says invalid subleaves return 0. We had been relying on that behavior instead of checking the max sublef number. It appears that some Sandy Bridge CPUs return at least the subleaf 0 EDX value for subleaf 1. Best guess is that this is a bug in a microcode patch since all of the bits we're seeing set in EDX were introduced after Sandy Bridge was originally released. This is causing avxvnniint16 to be incorrectly enabled with -march=native on these CPUs. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Check EAX for valid subleaf before use CPUID.
2023-08-02i386: refactor macros.Hu, Lin11-5/+5
gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Change OPTION_MASK_ISA2_AMX_TILE to OPTION_MASK_ISA2_AMX_TILE_SET. (OPTION_MASK_ISA2_AMX_BF16_SET): Ditto (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto (OPTION_MASK_ISA2_AMX_COMPLEX_SET): Ditto (OPTION_MASK_ISA_ABM_SET): Change OPTION_MASK_ISA_POPCNT to OPTION_MASK_ISA_POPCNT_SET. Signed-off-by: Hu, Lin1 <lin1.hu@intel.com>
2023-07-26[PATCH 1/5] [RISC-V] Recognize Zicond extensionXiao Zeng1-0/+3
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * config/riscv/riscv-opts.h (MASK_ZICOND): New mask. (TARGET_ZICOND): New target. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/attribute-21.c: New test. Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-07-24[committed] Use single quote rather than backquote in RISC-V diagnosticJeff Law1-3/+3
Similar to the other patch this morning, this fixes a warning that was causing the RISC-V bootstrap to fail. In this case the diagnostic used a backquote. This changes it to a simple single quote which the diagnostic framework won't complain about. Committed to the trunk. gcc/ * common/config/riscv/riscv-common.cc (riscv_subset_list::add): Use single quote rather than backquote in diagnostic.
2023-07-19RISC-V: Throw compilation error for unknown extensionsLehua Ding1-12/+56
This tiny patch add a check for extension starts with 'z' or 's' in `-march` option. Currently this unknown extension will be passed to the assembler, which then reports an error. With this patch, the compiler will throw a compilation error if the extension starts with 'z' or 's' is not a standard sub-extension or supervisor extension. Along with two extra changes. The first is to reduce repeated errors, which are currently reported at least twice. The second is to report as many mistakes as possible. e.g.: Run `riscv64-unknown-elf-gcc -march=rv64gvcw_zvl128_s123_x123 -mabi=lp64d a.c` will throw these error: riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': ISA string is not in canonical order. 'c' riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'w' is unsupported standard single letter extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'zvl128' start with `z` but is unsupported standard extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 's123' start with `s` but is unsupported standard supervisor extension riscv64-unknown-elf-gcc: error: '-march=rv64gcv_zvl128_s123': extension 'x123' start with `x` but is unsupported non-standard extension gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_supported_std_ext): Init. (standard_extensions_p): Add check. (riscv_subset_list::add): Just return NULL if it failed before. (riscv_subset_list::parse_std_ext): Continue parse when find a error (riscv_subset_list::parse): Just return NULL if it failed before. * config/riscv/riscv-subset.h (class riscv_subset_list): Add field. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-2.c: Update -march. * gcc.target/riscv/arch-3.c: Ditto. * gcc.target/riscv/arch-5.c: Ditto. * gcc.target/riscv/arch-8.c: Ditto. * gcc.target/riscv/attribute-10.c: Ditto. * gcc.target/riscv/attribute-18.c: Ditto. * gcc.target/riscv/attribute-19.c: Ditto. * gcc.target/riscv/attribute-8.c: Ditto. * gcc.target/riscv/attribute-9.c: Ditto. * gcc.target/riscv/pr102957.c: Ditto. * gcc.target/riscv/arch-22.cc: New test.
2023-07-17RISC-V: Ensure all implied extensions are included [PR110696]Lehua Ding1-3/+30
This patch fix target/PR110696, recursively add all implied extensions. PR target/110696 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions. (riscv_subset_list::check_implied_ext): Add new method. (riscv_subset_list::parse): Call checker check_implied_ext. * config/riscv/riscv-subset.h: Add new method. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-20.c: New test. * gcc.target/riscv/pr110696.c: New test. Signed-off-by: Lehua Ding <lehua.ding@rivai.ai>
2023-07-17Initial Lunar Lake, Arrow Lake and Arrow Lake S SupportMo, Zewei3-0/+27
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Lunar Lake, Arrow Lake and Arrow Lake S. * common/config/i386/i386-common.cc: (processor_name): Add arrowlake. (processor_alias_table): Add arrow lake, arrow lake s and lunar lake. * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_ARROWLAKE and INTEL_COREI7_ARROWLAKE_S. * config.gcc: Add -march=arrowlake and -march=arrowlake-s. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle arrowlake-s. * config/i386/i386-c.cc (ix86_target_macros_internal): Add arrowlake. * config/i386/i386-options.cc (m_ARROWLAKE): New. (processor_cost_table): Add arrowlake. * config/i386/i386.h (enum processor_type): Add PROCESSOR_ARROWLAKE. * config/i386/x86-tune.def: Add m_ARROWLAKE. * doc/extend.texi: Add arrowlake and arrowlake-s. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Add arrowlake and arrowlake-s. * gcc.target/i386/funcspec-56.inc: Handle new march.
2023-07-17Support Intel SM4Haochen Jiang4-1/+23
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle -msm4. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM4. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sm4. * config.gcc: Add sm4intrin.h. * config/i386/cpuid.h (bit_SM4): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM4__. * config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4). * config/i386/i386-options.cc (isa2_opts): Add -msm4. (ix86_valid_target_attribute_inner_p): Handle sm4. * config/i386/i386.opt: Add option -msm4. * config/i386/immintrin.h: Include sm4intrin.h * config/i386/sse.md (vsm4key4_<mode>): New define insn. (vsm4rnds4_<mode>): Ditto. * doc/extend.texi: Document sm4. * doc/invoke.texi: Document -msm4. * doc/sourcebuild.texi: Document target sm4. * config/i386/sm4intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm4. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm4. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm4. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm4): New. * gcc.target/i386/sm4-1.c: New test. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/sm4key4-2.c: Ditto. * gcc.target/i386/sm4rnds4-2.c: Ditto.
2023-07-17Support Intel SHA512Haochen Jiang4-1/+22
gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512. (ix86_handle_option): Handle -msha512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SHA512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sha512. * config.gcc: Add sha512intrin.h. * config/i386/cpuid.h (bit_SHA512): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SHA512__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI. * config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512). * config/i386/i386-options.cc (isa2_opts): Add -msha512. (ix86_valid_target_attribute_inner_p): Handle sha512. * config/i386/i386.opt: Add option -msha512. * config/i386/immintrin.h: Include sha512intrin.h. * config/i386/sse.md (vsha512msg1): New define insn. (vsha512msg2): Ditto. (vsha512rnds2): Ditto. * doc/extend.texi: Document sha512. * doc/invoke.texi: Document -msha512. * doc/sourcebuild.texi: Document target sha512. * config/i386/sha512intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msha512. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msha512. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sha512. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sha512): New. * gcc.target/i386/sha512-1.c: New test. * gcc.target/i386/sha512-check.h: Ditto. * gcc.target/i386/sha512msg1-2.c: Ditto. * gcc.target/i386/sha512msg2-2.c: Ditto. * gcc.target/i386/sha512rnds2-2.c: Ditto.
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