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2023-07-26[PATCH 1/5] [RISC-V] Recognize Zicond extensionXiao Zeng1-0/+3
2023-07-24[committed] Use single quote rather than backquote in RISC-V diagnosticJeff Law1-3/+3
2023-07-19RISC-V: Throw compilation error for unknown extensionsLehua Ding1-12/+56
2023-07-17RISC-V: Ensure all implied extensions are included [PR110696]Lehua Ding1-3/+30
2023-07-17Initial Lunar Lake, Arrow Lake and Arrow Lake S SupportMo, Zewei3-0/+27
2023-07-17Support Intel SM4Haochen Jiang4-1/+23
2023-07-17Support Intel SHA512Haochen Jiang4-1/+22
2023-07-17Support Intel SM3Haochen Jiang4-1/+23
2023-07-17Support Intel AVX-VNNI-INT16Kong Lingling4-1/+26
2023-07-14RISC-V: Recognized zihintntl extensionsMonk Chiang1-0/+4
2023-07-12Initial Granite Rapids D SupportMo, Zewei3-1/+11
2023-07-04RISC-V: Add support for vector crypto extensionsChristoph Müllner1-0/+55
2023-06-29x86: Update model values for Alderlake, Rocketlake and Raptorlake.Cui, Lili1-2/+1
2023-06-19avr: Fix wrong array bounds warning on SFR accessSenthil Kumar Selvaraj1-6/+0
2023-06-01RISC-V: Introduce vfloat16m{f}*_t and their machine mode.Pan Li1-0/+2
2023-05-31RISC-V: Add ZVFH extension to the -march= optionPan Li1-0/+4
2023-05-29RISC-V: Add ZVFHMIN extension to the -march= optionPan Li1-0/+3
2023-05-17RISC-V: Remove trailing spaces on lines.Jin Ma1-1/+1
2023-05-16rs6000: Enable REE pass by default“Ajit Kumar Agarwal”1-0/+2
2023-05-16RISC-V: Fix wrong select_kind in riscv_compute_multilibKito Cheng1-3/+3
2023-05-12RISC-V: Suppress unused parameter warning in riscv-common.ccKito Cheng1-9/+3
2023-05-08RISC-V: Handle multi-lib path correclty for linuxKito Cheng1-40/+88
2023-04-20i386: Share AES xmm intrin with VAESHaochen Jiang1-1/+4
2023-04-20i386: Add PCLMUL dependency for VPCLMULQDQHaochen Jiang1-3/+6
2023-04-20i386: Add AVX512BW dependency to AVX512VBMI2Haochen Jiang1-3/+2
2023-04-20i386: Add AVX512BW dependency to AVX512BITALGHaochen Jiang1-4/+4
2023-04-18RISC-V: Adjust the parsing order of extensions to be consistent with riscv-sp...Jin Ma1-6/+6
2023-04-10Support Intel AMX-COMPLEXHaochen Jiang4-1/+23
2023-04-04riscv: Fix bootstrap [PR109384]Jakub Jelinek1-4/+3
2023-03-29RISC-V: Add Z*inx imcompatible check in gccJiawei1-0/+5
2023-03-15riscv: Add basic XThead* vendor extension supportChristoph Müllner1-0/+26
2023-02-13arc: Don't use millicode thunks unless asked for.Claudiu Zissulescu1-1/+0
2023-02-12RISC-V: Add vmulh C/C++ supportJu-Zhe Zhong1-0/+1
2023-02-09i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]Jakub Jelinek1-16/+9
2023-02-02RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.Jin Ma1-1/+4
2023-02-01AArch64: Fix native detection in the presence of mandatory features which don...Tamar Christina1-5/+17
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab1-0/+4
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo1-6/+7
2023-01-16Update copyright years.Jakub Jelinek55-55/+55
2023-01-13arm: Add cde feature support for Cortex-M55 CPU.Srinath Parvathaneni1-9/+12
2023-01-05Add AMD znver4 instruction reservationsTejas Joshi1-1/+1
2023-01-04Initial Emeraldrapids SupportHu, Lin12-0/+4
2023-01-04i386: Remove Meteorlake's family_modelHu, Lin11-1/+0
2022-12-27Fixed typo in RISCVjinma1-1/+1
2022-12-27rs6000: Rework option -mpowerpc64 handling [PR106680]Kewen Lin1-11/+0
2022-11-24i386: Only enable small loop unrolling in backend [PR 107692]Hongyu Wang1-0/+8
2022-11-14Revert "sphinx: port .def files to RST"Martin Liska1-14/+14
2022-11-14i386: Add AMX-TILE dependency for AMX related ISAsHaochen Jiang1-4/+9
2022-11-14Enable small loop unrolling for O2Hongyu Wang1-0/+1
2022-11-09sphinx: port .def files to RSTMartin Liska1-14/+14