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2020-09-17If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx.liuhongt1-2/+3
2020-09-10aarch64: Add support for Armv8-RAlex Coplan1-2/+5
2020-09-08MSP430: Use enums to handle -mcpu= valuesJozef Lawrynowicz1-23/+3
2020-08-28Fix: AVX512VP2INTERSECT should imply AVX512DQ.liuhongt1-2/+2
2020-08-19x86: Detect Rocket Lake and Alder LakeH.J. Lu1-0/+10
2020-07-10Initial Sapphire Rapids and Alder Lake support from ISA r40Cui,Lili3-0/+16
2020-07-01RISC-V: Preserve arch version info during normalizing arch stringKito Cheng1-24/+46
2020-06-24x86: Remove brand ID check for Intel processorsH.J. Lu1-7/+5
2020-06-24x86: Add Cooper Lake detection with AVX512BF16H.J. Lu1-1/+9
2020-06-24x86: Share _isa_names_table and use cpuinfo.hH.J. Lu1-0/+163
2020-06-24x86: Move cpuinfo.h from libgcc to common/config/i386H.J. Lu2-0/+942
2020-06-24x86: Fold arch_names_table into processor_alias_tableH.J. Lu2-90/+283
2020-06-08[arm] (header usage fix) include c++ algorithm header via system.hChristophe Lyon1-1/+1
2020-05-21Add outline-atomics to target attribute.Martin Liska1-0/+4
2020-05-19RISC-V: Handle implied extension for -march parser.Kito Cheng1-10/+75
2020-05-19RISC-V: Update march parserKito Cheng1-20/+20
2020-05-06Enable TARGET_TSXLDTRK for GCC support.liuhongt1-0/+15
2020-05-06Enable GCC support for SERIALIZEliuhongt1-0/+15
2020-04-29[gcn] Set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282]Thomas Schwinge1-0/+9
2020-04-27rs6000: enable -fweb for small loops unrollingguojiufu1-3/+3
2020-04-03AArch64: Fix options canonicalization for assemblerTamar Christina1-1/+16
2020-03-16[ARM][GCC][2/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni1-1/+2
2020-02-20Remove trailing | in help message.Martin Liska1-3/+3
2020-02-13arc: Don't use if-conversion when optimizing for size.Claudiu Zissulescu1-0/+1
2020-02-13[ARC] Deprecate q-class option.Claudiu Zissulescu1-1/+0
2020-01-09avr-common.c (avr_option_optimization_table): Set -fsplit-wide-types-early.Georg-Johann Lay1-0/+2
2020-01-01Update copyright years.Jakub Jelinek54-54/+54
2019-12-17re PR target/92962 (Documentation: x86 Options - znver2 missing RDPID and WBN...Jakub Jelinek1-5/+5
2019-12-09Use OPTION_MASK_ISA2_$target_[SET,UNSET, ] to indicate those forHongtao Liu1-113/+113
2019-11-16Delete common/config/powerpcspeSegher Boessenkool1-321/+0
2019-11-12Remove option_default_params and option_validate_param hooks.Martin Liska9-130/+17
2019-11-12Remove set_default_param_value from documentation.Martin Liska1-4/+2
2019-11-12Remove gcc/params.* files.Martin Liska6-6/+0
2019-11-12Apply mechanical replacement (generated patch).Martin Liska5-16/+13
2019-11-11rs6000: Refine small loop unroll in loop_unroll_adjust hookJiufu Guo1-1/+8
2019-11-07Support 64-bit double and 64-bit long double configurations.Georg-Johann Lay1-0/+95
2019-10-28rs6000: Enable limited unrolling at -O2Jiufu Guo1-0/+1
2019-10-17Fix breakage introduced by r276985.Georg-Johann Lay1-0/+5
2019-10-10S/390: Add support for z15 as CPU name.Andreas Krebbel1-2/+2
2019-09-09GCC port for eBPFJose E. Marchesi1-0/+55
2019-09-03Remove Cell Broadband Engine SPU targetsUlrich Weigand1-56/+0
2019-08-20Add TIGERLAKE and COOPERLAKE to GCC.Hongtao Liu1-0/+4
2019-07-31RISC-V: Raise error on unexpected ISA string at end.Maxim Blinov1-0/+7
2019-07-23i386-common.c: Use PROCESSOR_ZNVER2 scheduler for znver2.Jan Hubicka1-1/+1
2019-07-08subreg: Add -fsplit-wide-types-early (PR88233)Segher Boessenkool1-0/+2
2019-06-26Enable GCC support for AVX512_VP2INTERSECT which will be in tigerlaker.Hongtao Liu1-1/+21
2019-06-12Initial TI PRU GCC portDimitar Dimitrov1-0/+36
2019-05-28Add GCC support to ENQCMD.Xuepeng Guo1-0/+15
2019-05-24[aarch64] Change two function declaration typesMatthew Malcomson1-1/+1
2019-05-22[aarch64] Introduce flags for SVE2.Matthew Malcomson1-16/+19
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