| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-04-27 | Synchronize Rocket Lake's processor_names and processor_cost_table with proce... | Cui,Lili | 1 | -1/+1 |
| 2021-04-21 | x86: Add -mmwait for -mgeneral-regs-only | H.J. Lu | 1 | -0/+15 |
| 2021-04-12 | Add rocketlake to gcc. | Cui,Lili | 3 | -2/+13 |
| 2021-04-12 | Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2 | Cui,Lili | 1 | -0/+1 |
| 2021-03-24 | i386: fix -march=amd crash | Martin Liska | 1 | -1/+1 |
| 2021-03-23 | RISC-V: Add riscv{32,64}be with big endian as default | Marcus Comstedt | 1 | -0/+5 |
| 2021-03-09 | arm: fix bootstrap failure following automatic mode selection patch | Richard Earnshaw | 1 | -1/+1 |
| 2021-03-03 | arm: Ignore --with-mode when CPU only supports one instruction set. | Richard Earnshaw | 1 | -6/+43 |
| 2021-03-02 | IBM Z: arch14: Add command line options | Andreas Krebbel | 1 | -0/+4 |
| 2021-01-28 | RISC-V: Fix -march option parsing when extension exists. | Xing GUO | 1 | -3/+1 |
| 2021-01-14 | i386: Resolve variable shadowing in i386-options.c [PR98671] | Uros Bizjak | 1 | -1/+1 |
| 2021-01-08 | RISC-V: Implement new style of architecture extension test macros. | Kito Cheng | 1 | -0/+5 |
| 2021-01-08 | RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h | Kito Cheng | 1 | -66/+1 |
| 2021-01-04 | Update copyright years. | Jakub Jelinek | 57 | -57/+57 |
| 2020-12-11 | Fix feature check for HRESET/AVX_VNNI/UINTR | Hongyu | 1 | -10/+15 |
| 2020-12-05 | X86_64: Enable support for next generation AMD Zen3 CPU. | Venkataramanan Kumar | 3 | -1/+34 |
| 2020-11-18 | RISC-V: Support version controling for ISA standard extensions | Kito Cheng | 1 | -72/+215 |
| 2020-11-18 | RISC-V: Support zicsr and zifencei extension for -march. | Kito Cheng | 1 | -0/+6 |
| 2020-11-18 | RISC-V: Handle implied extension in canonical ordering. | Kito Cheng | 1 | -5/+172 |
| 2020-11-11 | Support Intel AVX VNNI | liuhongt | 4 | -1/+23 |
| 2020-11-06 | RISC-V: Mark non-export symbol static and const in riscv-common.c | Kito Cheng | 1 | -2/+2 |
| 2020-11-02 | RISC-V: Check multiletter extension has more than 1 letter | Kito Cheng | 1 | -0/+8 |
| 2020-10-29 | Enable GCC to support Intel Key Locker ISA | liuhongt | 4 | -18/+93 |
| 2020-10-27 | RISC-V: Refine riscv_parse_arch_string | Kito Cheng | 1 | -33/+51 |
| 2020-10-15 | RISC-V: Add support for -mcpu option. | Kito Cheng | 1 | -5/+86 |
| 2020-10-15 | Enable Intel HRESET Instruction | Hongyu Wang | 4 | -0/+20 |
| 2020-10-15 | Enable gcc support for UINTR | liuhongt | 4 | -0/+19 |
| 2020-10-01 | PR target/97250: i386: Add support for x86-64-v2, x86-64-v3, x86-64-v4 levels... | Florian Weimer | 1 | -3/+7 |
| 2020-09-28 | Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16. | liuhongt | 4 | -0/+72 |
| 2020-09-17 | If -mavx implies -mxsave, then -mno-xsave should imply -mno-avx. | liuhongt | 1 | -2/+3 |
| 2020-09-10 | aarch64: Add support for Armv8-R | Alex Coplan | 1 | -2/+5 |
| 2020-09-08 | MSP430: Use enums to handle -mcpu= values | Jozef Lawrynowicz | 1 | -23/+3 |
| 2020-08-28 | Fix: AVX512VP2INTERSECT should imply AVX512DQ. | liuhongt | 1 | -2/+2 |
| 2020-08-19 | x86: Detect Rocket Lake and Alder Lake | H.J. Lu | 1 | -0/+10 |
| 2020-07-10 | Initial Sapphire Rapids and Alder Lake support from ISA r40 | Cui,Lili | 3 | -0/+16 |
| 2020-07-01 | RISC-V: Preserve arch version info during normalizing arch string | Kito Cheng | 1 | -24/+46 |
| 2020-06-24 | x86: Remove brand ID check for Intel processors | H.J. Lu | 1 | -7/+5 |
| 2020-06-24 | x86: Add Cooper Lake detection with AVX512BF16 | H.J. Lu | 1 | -1/+9 |
| 2020-06-24 | x86: Share _isa_names_table and use cpuinfo.h | H.J. Lu | 1 | -0/+163 |
| 2020-06-24 | x86: Move cpuinfo.h from libgcc to common/config/i386 | H.J. Lu | 2 | -0/+942 |
| 2020-06-24 | x86: Fold arch_names_table into processor_alias_table | H.J. Lu | 2 | -90/+283 |
| 2020-06-08 | [arm] (header usage fix) include c++ algorithm header via system.h | Christophe Lyon | 1 | -1/+1 |
| 2020-05-21 | Add outline-atomics to target attribute. | Martin Liska | 1 | -0/+4 |
| 2020-05-19 | RISC-V: Handle implied extension for -march parser. | Kito Cheng | 1 | -10/+75 |
| 2020-05-19 | RISC-V: Update march parser | Kito Cheng | 1 | -20/+20 |
| 2020-05-06 | Enable TARGET_TSXLDTRK for GCC support. | liuhongt | 1 | -0/+15 |
| 2020-05-06 | Enable GCC support for SERIALIZE | liuhongt | 1 | -0/+15 |
| 2020-04-29 | [gcn] Set 'UI_NONE' for 'TARGET_EXCEPT_UNWIND_INFO' [PR94282] | Thomas Schwinge | 1 | -0/+9 |
| 2020-04-27 | rs6000: enable -fweb for small loops unrolling | guojiufu | 1 | -3/+3 |
| 2020-04-03 | AArch64: Fix options canonicalization for assembler | Tamar Christina | 1 | -1/+16 |
