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2017-03-24S/390: arch12: Add arch12 option.Andreas Krebbel1-1/+4
2017-03-13[ARC] Code size modifications.Claudiu Zissulescu1-0/+1
2017-02-18re PR target/79569 (Unrecognized command line option ‘-m3dnowa’)Jakub Jelinek1-1/+13
2017-02-17i386-common.c (OPTION_MASK_ISA_RDPID_SET): New.Julia Koval1-0/+15
2017-02-06RISC-V Port: gccPalmer Dabbelt1-0/+131
2017-01-11i386-common.c (OPTION_MASK_ISA_SGX_UNSET): New.Julia Koval1-0/+15
2017-01-11[arm] Replace command-line option .def files with single definition fileRichard Earnshaw1-13/+1
2017-01-10Enable AVX-512 VPOPCNTD/VPOPCNTQ instructions.Andrew Senkevich1-0/+19
2017-01-09re PR translation/79019 (translatable string typo in cif-code.def:141)Jakub Jelinek1-1/+1
2017-01-06Make MicroBlaze support DWARF EH (old Xilinx patch, needed for glibc build).Edgar E. Iglesias1-3/+0
2017-01-01Update copyright years.Jakub Jelinek49-49/+49
2016-12-21re PR rtl-optimization/11488 (Pre-regalloc scheduling severely worsens perfor...Pat Haugen1-0/+2
2016-12-15[arm] Remove remaining references to arm feature setsRichard Earnshaw1-2/+2
2016-12-15[arm] Rework arm-common to use new feature bits.Richard Earnshaw1-4/+19
2016-12-15This patch adds the new ISA data structures.Richard Earnshaw1-2/+2
2016-12-15We start out by separating the 'tuning flags' in a CPU or architecture...Richard Earnshaw1-2/+2
2016-12-14aarch64-cores.def: Add -1 as the variant to all of the cores.Andrew Pinski1-1/+1
2016-12-12Define arm_arch_core_flags in a single fileThomas Preud'homme1-0/+20
2016-11-29arc-common.c (arc_handle_option): Remove unused variables.Jeff Law1-2/+0
2016-11-24sparc-common.c (sparc_option_optimization_table): Enable REE at -O2 and higher.Eric Botcazou1-0/+2
2016-11-18[ARM] Optional -mthumb for Thumb only targetsThomas Preud'homme1-0/+23
2016-11-17Enable AVX512_4FMAPS and AVX512_4VNNIW instructionsKirill Yukhin1-0/+40
2016-11-15[ARC] New option handling, refurbish multilib support.Claudiu Zissulescu1-52/+17
2016-10-13Move MEMMODEL_* from coretypes.h to memmodel.hThomas Preud'homme7-0/+7
2016-10-10[ARC] Disable compact casesi patterns for arcv2Claudiu Zissulescu1-1/+0
2016-10-07aarch64-arches.def (AARCH64_ARCH): #undef at the end.Andrew Pinski1-3/+0
2016-10-05Delete x86 deprecated pcommit instruction supportAndrew Senkevich1-15/+0
2016-08-04re PR target/70677 (Suboptimal cond on AVR: unneeded stack frame)Georg-Johann Lay1-0/+3
2016-06-21remove mep-* supportTrevor Saunders1-89/+0
2016-05-25re PR target/70738 (Add -mgeneral-regs-only option)Uros Bizjak1-0/+21
2016-05-22revert: re PR target/70738 (Add -mgeneral-regs-only option)Uros Bizjak1-20/+0
2016-05-20Add -mgeneral-regs-only optionH.J. Lu1-0/+20
2016-04-29longlong.h (umul_ppmm): Remove SHMEDIA checks.Oleg Endo1-7/+0
2016-04-28arc-common.c (arc_handle_option): Add NPS400 support, setup defaults.Andrew Burgess1-0/+4
2016-04-28sh-common.c: Remove SH5 support.Oleg Endo1-30/+0
2016-04-11[Patch AArch64 2/3] Rework the code to print extension strings (pr70133)James Greenhalgh1-13/+103
2016-03-10[AArch64] Fix thinko in handling of -momit-leaf-frame-pointer optionKyrylo Tkachov1-1/+1
2016-02-15S/390: Add -fsplit-stack supportMarcin Kościelnicki1-0/+14
2016-01-22system.h (string, algorithm): Include only conditionally.Michael Matz1-0/+1
2016-01-04Update copyright years.Jakub Jelinek50-50/+50
2015-12-24Introduce support for PKU instructions.Kirill Yukhin1-0/+15
2015-12-06support for AMD clzero isa.Victoria Stepanyan1-0/+16
2015-12-04gcc * config.gcc (extra_gcc_objs): Define for MSP430.Nick Clifton1-7/+3
2015-12-04[PATCH 1/2] S/390: Implement "target" attribute.Dominik Vogt1-18/+4
2015-11-11arc-common.c (arc_handle_option): Handle ARCv2 options.Claudiu Zissulescu1-1/+33
2015-11-07i386: Use the STC bb-reorder algorithm at -Os (PR67864)Segher Boessenkool1-0/+3
2015-10-20Properly handle -miamcu and -march=lakemontH.J. Lu1-15/+1
2015-10-20mn10300: Use the STC bb-reorder algorithm at -OsSegher Boessenkool1-0/+3
2015-09-10arc-common.c: Remove references to A5.Claudiu Zissulescu1-2/+1
2015-08-20[AArch64] Break -mcpu tie between the compiler and assemblerJames Greenhalgh1-22/+120
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