diff options
Diffstat (limited to 'gcc/testsuite')
167 files changed, 3280 insertions, 943 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 69f9b6e..f13a988 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,390 @@ +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/fmov-3-be.c: New test. + * gcc.target/aarch64/fmov-3-le.c: New test. + * gcc.target/aarch64/fmov-4-be.c: New test. + * gcc.target/aarch64/fmov-4-le.c: New test. + * gcc.target/aarch64/fmov-5-be.c: New test. + * gcc.target/aarch64/fmov-5-le.c: New test. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/fmov-1-be.c: New test. + * gcc.target/aarch64/fmov-1-le.c: New test. + * gcc.target/aarch64/fmov-2-be.c: New test. + * gcc.target/aarch64/fmov-2-le.c: New test. + +2025-05-16 Pengxuan Zheng <quic_pzheng@quicinc.com> + + PR target/100165 + * gcc.target/aarch64/and-be.c: New test. + * gcc.target/aarch64/and-le.c: New test. + +2025-05-16 Robert Dubner <rdubner@symas.com> + + * cobol.dg/group1/declarative_1.cob: Handle modified exception handling. + +2025-05-16 Andrew Pinski <quic_apinski@quicinc.com> + + * gcc.dg/pr78408-1.c: Update scan to forwprop1 only. + +2025-05-16 Jason Merrill <jason@redhat.com> + + * g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C: + Remove { target c++17 }. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Take + test name for the vx combine test data. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Leverage + the test name to identify the test data. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 2. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 1. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Add test cases + for vsub vx combine case 1 with GR2VR cost 0. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Add test cases + for vsub vx combine with GR2VR cost 15. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Add test cases + for vsub vx combine with GR2VR cost 1. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Diito. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Diito. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add vector sub + vx combine asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test + data for vector sub vx combine. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c: New test. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add + type and op name to generate test function name. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Refine the + test helper macros to avoid conflict. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h: Ditto. + +2025-05-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: ...here. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c: Move to... + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: ...here. + +2025-05-15 Jason Merrill <jason@redhat.com> + + * g++.dg/coroutines/co-await-syntax-09-convert.C: Add -fcoroutines. + * g++.dg/coroutines/co-await-syntax-10.C + * g++.dg/coroutines/co-await-syntax-11.C + * g++.dg/coroutines/co-await-void_type.C + * g++.dg/coroutines/co-return-warning-1.C + * g++.dg/coroutines/ramp-return-a.C + * g++.dg/coroutines/ramp-return-c.C: Likewise. + * g++.dg/coroutines/coroutines.exp: Removed. + * lib/g++-dg.exp: Start at C++20 for coroutines/ + +2025-05-15 Harald Anlauf <anlauf@gmx.de> + + PR fortran/85750 + * gfortran.dg/alloc_comp_auto_array_3.f90: Adjust scan counts. + * gfortran.dg/alloc_comp_class_3.f03: Remove bogus warnings. + * gfortran.dg/alloc_comp_class_4.f03: Likewise. + * gfortran.dg/allocate_with_source_14.f03: Adjust scan count. + * gfortran.dg/derived_constructor_comps_6.f90: Likewise. + * gfortran.dg/derived_result_5.f90: New test. + +2025-05-15 Robert Dubner <rdubner@symas.com> + + PR cobol/120251 + * cobol.dg/group1/check_88.cob: One final regex "." instead of "ß" + +2025-05-15 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/116546 + * gcc.dg/pr116546.c: New. + +2025-05-15 Andrew MacLeod <amacleod@redhat.com> + + PR tree-optimization/120277 + * gcc.dg/pr120277.c: New. + +2025-05-15 Robert Dubner <rdubner@symas.com> + + PR cobol/120251 + * cobol.dg/group1/check_88.cob: Ignore characters above 0x80. + * cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.cob: + Output HIGH-VALUE as hex, rather than as characters. + * cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out: + Likewise. + * cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.cob: Typo. + * cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.out: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_1.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_2.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_3.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_4.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_5-f.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_6.cob: Likewise. + * cobol.dg/group2/INSPECT_ISO_Example_7.cob: Likewise. + * cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.cob: New test. + * cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.out: New test. + +2025-05-15 Jeff Law <jlaw@ventanamicro.com> + + PR target/120223 + * gcc.target/riscv/pr120223.c: New test. + +2025-05-15 Patrick Palka <ppalka@redhat.com> + + PR c++/120161 + * g++.dg/template/unify13.C: New test. + +2025-05-15 Jason Merrill <jason@redhat.com> + + * lib/g++-dg.exp (g++-std-flags): Factor out of g++-dg-runtest. + * g++.dg/modules/modules.exp: Use it instead of a copy. + +2025-05-15 Richard Biener <rguenther@suse.de> + + * gcc.target/i386/pr110310.c: Adjust. + +2025-05-15 Richard Biener <rguenther@suse.de> + + * gcc.target/i386/vect-epilogues-1.c: New testcase. + * gcc.target/i386/vect-epilogues-2.c: Likewise. + * gcc.target/i386/vect-epilogues-3.c: Likewise. + * gcc.target/i386/vect-epilogues-4.c: Likewise. + * gcc.target/i386/vect-epilogues-5.c: Likewise. + 2025-05-14 Simon Martin <simon@nasilyan.com> PR c++/120126 diff --git a/gcc/testsuite/cobol.dg/group1/check_88.cob b/gcc/testsuite/cobol.dg/group1/check_88.cob index 4a7723e..f1d0685 100644 --- a/gcc/testsuite/cobol.dg/group1/check_88.cob +++ b/gcc/testsuite/cobol.dg/group1/check_88.cob @@ -3,25 +3,25 @@ *> { dg-output {\-> <\-(\n|\r\n|\r)} } *> { dg-output {\->"""<\-(\n|\r\n|\r)} } *> { dg-output {\->000<\-(\n|\r\n|\r)} } -*> { dg-output {\->ÿÿÿ<\-(\n|\r\n|\r)} } +*> { dg-output {\->.*<\-(\n|\r\n|\r)} } *> { dg-output { (\n|\r\n|\r)} } *> { dg-output {\-><\-(\n|\r\n|\r)} } *> { dg-output {\-> <\-(\n|\r\n|\r)} } *> { dg-output {\->""""<\-(\n|\r\n|\r)} } *> { dg-output {\->0000<\-(\n|\r\n|\r)} } -*> { dg-output {\->ÿÿÿÿ<\-(\n|\r\n|\r)} } +*> { dg-output {\->.*<\-(\n|\r\n|\r)} } *> { dg-output { (\n|\r\n|\r)} } *> { dg-output {There should be no garbage after character 32(\n|\r\n|\r)} } *> { dg-output {\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\*\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-(\n|\r\n|\r)} } -*> { dg-output {üüüüüüüüüüüüüüüüüüü Bundesstraße (\n|\r\n|\r)} } -*> { dg-output {üüüüüüüüüüüüüüüüüüü Bundesstraße (\n|\r\n|\r)} } +*> { dg-output {.* Bundesstra.e (\n|\r\n|\r)} } +*> { dg-output {.* Bundesstra.e (\n|\r\n|\r)} } *> { dg-output { (\n|\r\n|\r)} } *> { dg-output {There should be no spaces before the final quote(\n|\r\n|\r)} } -*> { dg-output {"üüüüüüüüüüüüüüüüüüü Bundesstraße"(\n|\r\n|\r)} } +*> { dg-output {".* Bundesstra.e"(\n|\r\n|\r)} } *> { dg-output { (\n|\r\n|\r)} } *> { dg-output { IsLow ""(\n|\r\n|\r)} } *> { dg-output { IsZero "000"(\n|\r\n|\r)} } -*> { dg-output { IsHi "ÿÿÿ"(\n|\r\n|\r)} } +*> { dg-output { IsHi ".*"(\n|\r\n|\r)} } *> { dg-output { IsBob "bob"(\n|\r\n|\r)} } *> { dg-output { IsQuote """""(\n|\r\n|\r)} } *> { dg-output { IsSpace " "(\n|\r\n|\r)} } diff --git a/gcc/testsuite/cobol.dg/group1/declarative_1.cob b/gcc/testsuite/cobol.dg/group1/declarative_1.cob index ec68e9c..744495a 100644 --- a/gcc/testsuite/cobol.dg/group1/declarative_1.cob +++ b/gcc/testsuite/cobol.dg/group1/declarative_1.cob @@ -1,14 +1,14 @@ *> { dg-do run } *> { dg-output {Turning EC\-ALL CHECKING OFF \-\- Expecting \+00\.00 from ACOS\(\-3\)(\n|\r\n|\r)} } -*> { dg-output { \+00\.00 TABL\(VSIX\) is 1(\n|\r\n|\r)} } +*> { dg-output { \+00\.00 TABL\(VSIX\) is 6(\n|\r\n|\r)} } *> { dg-output {Turning EC\-ARGUMENT\-FUNCTION CHECKING ON(\n|\r\n|\r)} } *> { dg-output { Expecting \+0\.00 and DECLARATIVE FOR EC\-ARGUMENT\-FUNCTION(\n|\r\n|\r)} } *> { dg-output { DECLARATIVE FOR EC\-ARGUMENT\-FUNCTION(\n|\r\n|\r)} } -*> { dg-output { \+00\.00 TABL\(VSIX\) is 1(\n|\r\n|\r)} } +*> { dg-output { \+00\.00 TABL\(VSIX\) is 6(\n|\r\n|\r)} } *> { dg-output {Turning EC\-ARGUMENT CHECKING ON(\n|\r\n|\r)} } *> { dg-output { Expecting \+0\.00 and DECLARATIVE FOR EC\-ARGUMENT\-FUNCTION(\n|\r\n|\r)} } *> { dg-output { DECLARATIVE FOR EC\-ARGUMENT\-FUNCTION(\n|\r\n|\r)} } -*> { dg-output { \+00\.00 TABL\(VSIX\) is 1(\n|\r\n|\r)} } +*> { dg-output { \+00\.00 TABL\(VSIX\) is 6(\n|\r\n|\r)} } *> { dg-output {Turning EC\-ALL CHECKING ON(\n|\r\n|\r)} } *> { dg-output { Expecting \+0\.00 and DECLARATIVE EC\-ARGUMENT\-FUNCTION(\n|\r\n|\r)} } *> { dg-output { Followed by DECLARATIVE EC\-ALL for TABL\(6\) access(\n|\r\n|\r)} } diff --git a/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.cob b/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.cob index 6fab992..a5ef3a8 100644 --- a/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.cob +++ b/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.cob @@ -81,12 +81,13 @@ 02 based-x pic x(24) value "I am I, Don Quixote". 02 based-9 pic 999 value 123. 02 based-p pointer value NULL. + 01 pval redefines based-var pointer. 01 allocated-pointer pointer. procedure division. display "allocate characters (ISO 2023 Rule 8: OPT_INIT if specified, otherwise defaultbyte, otherwise zero)" allocate 35 characters returning allocated-pointer set address of based-var to allocated-pointer - call "reporter" using based-var + display pval free allocated-pointer goback. end program prog-high. diff --git a/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out b/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out index c141fdf..ea05e96 100644 --- a/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out +++ b/gcc/testsuite/cobol.dg/group2/ALLOCATE_Rule_8_OPTION_INITIALIZE_with_figconst.out @@ -12,6 +12,5 @@ allocate characters (ISO 2023 Rule 8: OPT_INIT if specified, otherwise defaultb " " " " 0x2020202020202020 initialize high-value allocate characters (ISO 2023 Rule 8: OPT_INIT if specified, otherwise defaultbyte, otherwise zero) - (1) as allocated - "ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ" "¿¿¿" 0xffffffffffffffff +0xffffffffffffffff diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.cob index 2983cce..91440f5 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.cob @@ -1,27 +1,27 @@ *> { dg-do run } *> { dg-output-file "group2/INSPECT_CONVERTING_TO_figurative_constants.out" } - identification division. program-id. clouseau. data division. working-storage section. 01 item pic x(12). + 01 pitem redefines item pointer. procedure division. move all "abcd" to item inspect item converting "abcd" to low-values - display "low-values " space """" item """" + display "low-values " space """" pitem """" move all "abcd" to item inspect item converting "abcd" to spaces - display "spaces " space """" item """" + display "spaces " space """" pitem """" move all "abcd" to item inspect item converting "abcd" to zeros - display "zeros " space """" item """" + display "zeros " space """" pitem """" move all "abcd" to item inspect item converting "abcd" to quotes - display "quotes " space """" item """" + display "quotes " space """" pitem """" move all "abcd" to item inspect item converting "abcd" to high-values - display "high-values" space """" item """" + display "high-values" space """" pitem """" goback. end program clouseau. diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.out b/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.out index 7de6e48..23ce49b 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.out +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_CONVERTING_TO_figurative_constants.out @@ -1,6 +1,6 @@ -low-values "" -spaces " " -zeros "000000000000" -quotes """""""""""""" -high-values "ÿÿÿÿÿÿÿÿÿÿÿÿ" +low-values "0x0000000000000000" +spaces "0x2020202020202020" +zeros "0x3030303030303030" +quotes "0x2222222222222222" +high-values "0xffffffffffffffff" diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_1.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_1.cob index 1bbdea4..2f306f1 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_1.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_1.cob @@ -25,7 +25,7 @@ Move ' EFABDBCGABEFGG 0301010005TUXYXVWRXYZZPZ' to row(1). Move ' BABABC 0200000101SXYXYZ' to row(3). Move ' BBBC 0001000200SSVW' to row(5). -` + compute rowlim = 2*rows - 1 Display ' INPUT C0 C1 C2 C3 C4 OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_2.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_2.cob index a464101..0e4297d 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_2.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_2.cob @@ -25,7 +25,7 @@ *> the observed outputs Move ' BBB 0300ZZZ' to row(1). Move ' ABA 0300ZZZ' to row(3). -` + compute rowlim = 2*rows - 1 Display ' INPUT C0 C1 OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_3.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_3.cob index 7111e9c..0b6c00c 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_3.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_3.cob @@ -19,7 +19,7 @@ Move ' ADDDDA 000005AZZZZZ' to row(5). Move ' CDDDDC 000000CDDDDC' to row(7). Move ' BDBBBDB 000300BDWWWDB' to row(9). -` + Display ' INPUT C0 C1 C2 OUTPUT' Display ' -------------------- -- -- -- --------------------' Perform Example-3 with test after diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_4.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_4.cob index 192e1a8..03a0b07 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_4.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_4.cob @@ -24,7 +24,7 @@ *> Even-numbered rows are modified by the INSPECT statements and contain *> the observed outputs Move ' ABABABABC 01ABABXYABC' to row(1). -` + compute rowlim = 2*rows - 1 Display ' INPUT C0 C1 OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_5-f.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_5-f.cob index 0923720..5ef97e1 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_5-f.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_5-f.cob @@ -30,7 +30,7 @@ Move ' ABABBCAB 000106ABABBCXY' to row(1). Move ' ABDBABC 000001AVDBABC' to row(3). Move ' BCABCABD 010000BCABCAVD' to row(5). -` + compute rowlim = 2*rows - 1 Display ' INPUT C0 C1 C2 OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_6.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_6.cob index 75917a2..40cecfc 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_6.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_6.cob @@ -22,7 +22,7 @@ *> Even-numbered rows are modified by the INSPECT statements and contain *> the observed outputs Move ' AC"AEBDFBCD#AB"D AC"XEYXFYZX#AB"D' to row(1). -` + compute rowlim = 2*rows - 1 Display ' INPUT OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_7.cob b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_7.cob index ca2ae71..abf9eb9 100644 --- a/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_7.cob +++ b/gcc/testsuite/cobol.dg/group2/INSPECT_ISO_Example_7.cob @@ -27,7 +27,7 @@ Move ' 415-245-1212 415-245-1212' to row(1). Move ' 415-CH5-1212 415-??5-1212' to row(3). Move ' 20%Numeric 20%???????' to row(5). -` + compute rowlim = 2*rows - 1 Display ' INPUT OUTPUT' diff --git a/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.cob b/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.cob new file mode 100644 index 0000000..4bcc06c --- /dev/null +++ b/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.cob @@ -0,0 +1,24 @@ + *> { dg-do run } + *> { dg-output-file "group2/Multiple_INDEXED_BY_variables_with_the_same_name.out" } + IDENTIFICATION DIVISION. + PROGRAM-ID. prog. + DATA DIVISION. + WORKING-STORAGE SECTION. + 01 GROUP-1-TABLE. + 05 TABLE-LEVEL-1 VALUE "ABCDEFGHIJKLMNO". + 06 TABLE-ITEM PICTURE X OCCURS 15 TIMES INDEXED BY IND. + 88 EQUALS-M VALUE "M". + 01 GROUP-2-TABLE. + 05 TABLE-LEVEL-1 VALUE "abcdefghijklmno". + 06 TABLE-ITEM PICTURE X OCCURS 15 TIMES INDEXED BY IND. + 88 EQUALS-M VALUE "M". + PROCEDURE DIVISION. + set IND OF GROUP-1-TABLE to 2 + set IND OF GROUP-2-TABLE to 4 + display "The output should be ""Db""" + display "The output is " """" + TABLE-ITEM of GROUP-1-TABLE(IND OF GROUP-2-TABLE) + TABLE-ITEM of GROUP-2-TABLE(IND OF GROUP-1-TABLE) + """" + goback. + diff --git a/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.out b/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.out new file mode 100644 index 0000000..c4d70c9 --- /dev/null +++ b/gcc/testsuite/cobol.dg/group2/Multiple_INDEXED_BY_variables_with_the_same_name.out @@ -0,0 +1,3 @@ +The output should be "Db" +The output is "Db" + diff --git a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-09-convert.C b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-09-convert.C index dde0bab..deb3be1 100644 --- a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-09-convert.C +++ b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-09-convert.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17 -w" } +// { dg-additional-options "-std=c++17 -fcoroutines -w" } #include "coro.h" diff --git a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-10.C b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-10.C index 8304344..dfa24a8 100644 --- a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-10.C +++ b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-10.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17 -w" } +// { dg-additional-options "-std=c++17 -fcoroutines -w" } #include "coro.h" diff --git a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-11.C b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-11.C index 69810ab..acee888 100644 --- a/gcc/testsuite/g++.dg/coroutines/co-await-syntax-11.C +++ b/gcc/testsuite/g++.dg/coroutines/co-await-syntax-11.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17 -w" } +// { dg-additional-options "-std=c++17 -fcoroutines -w" } #include <utility> #include <type_traits> diff --git a/gcc/testsuite/g++.dg/coroutines/co-await-void_type.C b/gcc/testsuite/g++.dg/coroutines/co-await-void_type.C index 370068f..f35faaf 100644 --- a/gcc/testsuite/g++.dg/coroutines/co-await-void_type.C +++ b/gcc/testsuite/g++.dg/coroutines/co-await-void_type.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17 -fsyntax-only -w" } +// { dg-additional-options "-std=c++17 -fsyntax-only -fcoroutines -w" } #include <coroutine> diff --git a/gcc/testsuite/g++.dg/coroutines/co-return-warning-1.C b/gcc/testsuite/g++.dg/coroutines/co-return-warning-1.C index b2aaba1..ef3948c 100644 --- a/gcc/testsuite/g++.dg/coroutines/co-return-warning-1.C +++ b/gcc/testsuite/g++.dg/coroutines/co-return-warning-1.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17 -w" } +// { dg-additional-options "-std=c++17 -fcoroutines -w" } #include <coroutine> diff --git a/gcc/testsuite/g++.dg/coroutines/coroutines.exp b/gcc/testsuite/g++.dg/coroutines/coroutines.exp deleted file mode 100644 index 395e3f7..0000000 --- a/gcc/testsuite/g++.dg/coroutines/coroutines.exp +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (C) 2018-2025 Free Software Foundation, Inc. - -# Contributed by Iain Sandoe <iain@sandoe.co.uk> under contract to Facebook. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. - -# Test C++ coroutines, requires c++17; doesn't, at present, seem much -# point in repeating these for other versions. - -# Load support procs. -load_lib g++-dg.exp - -# If a testcase doesn't have special options, use these. -global DEFAULT_CXXFLAGS -if ![info exists DEFAULT_CXXFLAGS] then { - set DEFAULT_CXXFLAGS " -pedantic-errors -Wno-long-long" -} - -set DEFAULT_COROFLAGS $DEFAULT_CXXFLAGS -lappend DEFAULT_COROFLAGS "-std=c++20" - -dg-init - -# Run the tests. -# g++-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \ -# "" $DEFAULT_COROFLAGS - -foreach test [lsort [find $srcdir/$subdir {*.[CH]}]] { - if [runtest_file_p $runtests $test] { - set nshort [file tail [file dirname $test]]/[file tail $test] - verbose "Testing $nshort $DEFAULT_COROFLAGS" 1 - dg-test $test "" $DEFAULT_COROFLAGS - set testcase [string range $test [string length "$srcdir/"] end] - } -} - -# done. -dg-finish diff --git a/gcc/testsuite/g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C b/gcc/testsuite/g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C index 90a558d..5e3608b 100644 --- a/gcc/testsuite/g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C +++ b/gcc/testsuite/g++.dg/coroutines/pr94760-mismatched-traits-and-promise-prev.C @@ -1,5 +1,3 @@ -// { dg-do compile { target c++17 } } - #include "coro.h" // Test that we get matching types to traits and promise param diff --git a/gcc/testsuite/g++.dg/coroutines/ramp-return-a.C b/gcc/testsuite/g++.dg/coroutines/ramp-return-a.C index fcea6f9..543f92f 100644 --- a/gcc/testsuite/g++.dg/coroutines/ramp-return-a.C +++ b/gcc/testsuite/g++.dg/coroutines/ramp-return-a.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++14" } +// { dg-additional-options "-std=c++14 -fcoroutines" } // { dg-skip-if "requires hosted libstdc++ for vector in ramp-return.h" { ! hostedlib } } #include "ramp-return.h" diff --git a/gcc/testsuite/g++.dg/coroutines/ramp-return-c.C b/gcc/testsuite/g++.dg/coroutines/ramp-return-c.C index 0992924..d5ea3f9 100644 --- a/gcc/testsuite/g++.dg/coroutines/ramp-return-c.C +++ b/gcc/testsuite/g++.dg/coroutines/ramp-return-c.C @@ -1,4 +1,4 @@ -// { dg-additional-options "-std=c++17" } +// { dg-additional-options "-std=c++17 -fcoroutines" } // { dg-skip-if "requires hosted libstdc++ for vector in ramp-return.h" { ! hostedlib } } #define DELETE_COPY_CTOR 1 #include "ramp-return.h" diff --git a/gcc/testsuite/g++.dg/modules/modules.exp b/gcc/testsuite/g++.dg/modules/modules.exp index 81d0beb..73b5de1 100644 --- a/gcc/testsuite/g++.dg/modules/modules.exp +++ b/gcc/testsuite/g++.dg/modules/modules.exp @@ -36,7 +36,6 @@ if ![info exists DEFAULT_CXXFLAGS] then { set DEFAULT_CXXFLAGS " -pedantic-errors -Wno-long-long" } set DEFAULT_MODFLAGS $DEFAULT_CXXFLAGS -set MOD_STD_LIST { 17 2a 2b } dg-init @@ -261,44 +260,16 @@ proc srcdir {} { return $testdir } -# Return set of std options to iterate over, taken from g++-dg.exp & compat.exp +# Return set of std options to iterate over. proc module-init { src } { - set tmp [dg-get-options $src] - set option_list {} - set have_std 0 - set std_prefix "-std=c++" + set option_list [g++-std-flags $src] global extra_tool_flags set extra_tool_flags {} - global MOD_STD_LIST - - foreach op $tmp { - switch [lindex $op 0] { - "dg-options" { - set std_prefix "-std=gnu++" - if { [string match "*-std=*" [lindex $op 2]] } { - set have_std 1 - } - eval lappend extra_tool_flags [lindex $op 2] - } - "dg-additional-options" { - if { [string match "*-std=*" [lindex $op 2]] } { - set have_std 1 - } - eval lappend extra_tool_flags [lindex $op 2] - } - } - } - if { $have_std } { - lappend option_list "" - } elseif { [string match "*xtreme*" $src] } { + if { [llength $option_list] + && [string match "*xtreme*" $src] } { # Only run the xtreme tests once. - set x [lindex $MOD_STD_LIST end] - lappend option_list "${std_prefix}$x" - } else { - foreach x $MOD_STD_LIST { - lappend option_list "${std_prefix}$x" - } + set option_list [lrange [lsort $option_list] end end] } return $option_list diff --git a/gcc/testsuite/g++.dg/template/unify13.C b/gcc/testsuite/g++.dg/template/unify13.C new file mode 100644 index 0000000..ec7ca9d --- /dev/null +++ b/gcc/testsuite/g++.dg/template/unify13.C @@ -0,0 +1,18 @@ +// PR c++/120161 + +template<class T, class U> +struct mp_list { }; + +template<class T> +struct Wrap { struct type { }; }; + +struct A : mp_list<Wrap<int>::type, void> + , mp_list<Wrap<long>::type, void> { }; + +template<class U> +void f(mp_list<Wrap<int>::type, U>*); + +int main() { + A a; + f(&a); +} diff --git a/gcc/testsuite/gcc.dg/pr116546.c b/gcc/testsuite/gcc.dg/pr116546.c new file mode 100644 index 0000000..b82dc27 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr116546.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-evrp" } */ + +extern long foo (void); +extern long bar (void); + +long +test1 (long n) +{ + n &= 7; + if (n == 4) { + if (n & 4) + return foo (); + else + return bar (); + } + return 0; +} + +long +test2 (long n) +{ + n &= 7; + if (n > 4) { + if (n & 4) + return foo (); + else + return bar (); + } + return 0; +} + +long +test3 (long n) +{ + n &= 7; + if (n >= 4) { + if (n & 4) + return foo (); + else + return bar (); + } + return 0; +} + +/* { dg-final { scan-tree-dump-not "bar" "evrp" } } */ diff --git a/gcc/testsuite/gcc.dg/pr120277.c b/gcc/testsuite/gcc.dg/pr120277.c new file mode 100644 index 0000000..f291e92 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr120277.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int a, b; +int c(int d, long e) { + switch (d) { + case 129: + a = 1; + case 128: + break; + default: + return 1; + } + *(int *)e = 0; +} +void f(int d, long e) { c(d, e); } +void g() { + int h = b * sizeof(int); + f(h + 7, h); +} +void main() {} diff --git a/gcc/testsuite/gcc.dg/pr78408-1.c b/gcc/testsuite/gcc.dg/pr78408-1.c index a2d9306..feb9180 100644 --- a/gcc/testsuite/gcc.dg/pr78408-1.c +++ b/gcc/testsuite/gcc.dg/pr78408-1.c @@ -1,8 +1,7 @@ /* PR c/78408 */ /* { dg-do compile { target size32plus } } */ /* { dg-options "-O2 -fdump-tree-ccp-details -fdump-tree-forwprop-details" } */ -/* { dg-final { scan-tree-dump-times "after previous" 1 "ccp1" } } */ -/* { dg-final { scan-tree-dump-times "after previous" 16 "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times "after previous" 17 "forwprop1" } } */ struct S { char a[33]; }; struct T { char a[65536]; }; diff --git a/gcc/testsuite/gcc.target/aarch64/and-be.c b/gcc/testsuite/gcc.target/aarch64/and-be.c new file mode 100644 index 0000000..7457dd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/and-be.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + + +/* +** f_v4hi: +** movi v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 1, 6, 3 }); +} + +/* +** g_v4hi: +** mvni v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 5, 2, 7 }); +} + +/* +** f_v8hi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 2, 5 }); +} + +/* +** g_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 1, 5, 3, 7 }); +} + +/* +** h_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 7, 1, 6, 3 }); +} + +/* +** f_v4sf: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 6, 2, 7 }); +} + +/* +** f_v8qi: +** movi d([0-9]+), 0xff00ff00ff000000 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v16qi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 16, 1, 17, 3, 18, 5, 19, 7, 20, 9, 21, 11, 22, 13, 23, 24 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/and-le.c b/gcc/testsuite/gcc.target/aarch64/and-le.c new file mode 100644 index 0000000..398813b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/and-le.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + + +/* +** f_v4hi: +** mvni v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 1, 6, 3 }); +} + +/* +** g_v4hi: +** movi v([0-9]+).2s, 0xff, msl 8 +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 5, 2, 7 }); +} + +/* +** f_v8hi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v4si: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 2, 5 }); +} + +/* +** g_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 1, 5, 3, 7 }); +} + +/* +** h_v4si: +** movi v([0-9]+).2d, 0xffffffff00000000 +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 7, 1, 6, 3 }); +} + +/* +** f_v4sf: +** movi v([0-9]+).2d, 0xffffffff +** and v0.16b, (?:v0.16b, v\1.16b|v\1.16b, v0.16b) +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 6, 2, 7 }); +} + +/* +** f_v8qi: +** movi d([0-9]+), 0xff00ff00ff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 8, 2, 9, 4, 10, 12, 11 }); +} + +/* +** f_v16qi: +** ... +** and v0.16b, (?:v0.16b, v[0-9]+.16b|v[0-9]+.16b, v0.16b) +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 16, 1, 17, 3, 18, 5, 19, 7, 20, 9, 21, 11, 22, 13, 23, 24 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c new file mode 100644 index 0000000..4227c67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-1-be.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef float v2sf __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef double v2df __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0, 0, 0xffff, 0xffff }; +} + +/* +** g_v4hi: +** movi d([0-9]+), 0xffff00000000ffff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0, 0, 0xffff, 0xffff }; +} + +/* +** g_v8hi: +** fmov d0, d0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0xffff, 0xffff, 0xffff, 0xffff }; +} + +/* +** f_v2si: +** fmov s0, s0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0, 0xffffffff }; +} + +/* +** f_v2di: +** fmov d0, d0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffffffffffffffff }; +} + +/* +** g_v2di: +** fmov s0, s0 +** ret +*/ +v2di +g_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffffffff }; +} + +/* +** f_v4si: +** fmov s0, s0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0, 0xffffffff }; +} + +/* +** h_v4si: +** fmov d0, d0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0xffffffff, 0xffffffff }; +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff }; +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c new file mode 100644 index 0000000..618702a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-1-le.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef float v2sf __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef double v2df __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0xffff, 0, 0 }; +} + +/* +** g_v4hi: +** movi d([0-9]+), 0xffff00000000ffff +** and v0.8b, (?:v0.8b, v\1.8b|v\1.8b, v0.8b) +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0xffff, 0, 0, 0, 0, 0, 0 }; +} + +/* +** g_v8hi: +** fmov d0, d0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0xffff, 0xffff, 0xffff, 0, 0, 0, 0 }; +} + +/* +** f_v2si: +** fmov s0, s0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0xffffffff, 0 }; +} + +/* +** f_v2di: +** fmov d0, d0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0xffffffffffffffff, 0 }; +} + +/* +** g_v2di: +** fmov s0, s0 +** ret +*/ +v2di +g_v2di (v2di x) +{ + return x & (v2di){ 0xffffffff, 0 }; +} + +/* +** f_v4si: +** fmov s0, s0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0xffffffff, 0, 0, 0 }; +} + +/* +** h_v4si: +** fmov d0, d0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return x & (v4si){ 0xffffffff, 0xffffffff, 0, 0 }; +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0 }; +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0xff, 0xff, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c new file mode 100644 index 0000000..1e38066 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-2-be.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v2di: +** fmov h0, h0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0, 0xffff }; +} + +/* +** f_v4si: +** fmov h0, h0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0, 0, 0, 0xffff }; +} + +/* +** f_v2si: +** fmov h0, h0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0, 0xffff }; +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0xffff }; +} + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0, 0, 0, 0xffff }; +} + +/* +** f_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0xff, 0xff }; +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0, 0, 0, 0, 0, 0, 0xff, 0xff }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c new file mode 100644 index 0000000..7627680 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-2-le.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef int v2si __attribute__ ((vector_size (8))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef long v2di __attribute__ ((vector_size (16))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v2di: +** fmov h0, h0 +** ret +*/ +v2di +f_v2di (v2di x) +{ + return x & (v2di){ 0xffff, 0 }; +} + +/* +** f_v4si: +** fmov h0, h0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return x & (v4si){ 0xffff, 0, 0, 0 }; +} + +/* +** f_v2si: +** fmov h0, h0 +** ret +*/ +v2si +f_v2si (v2si x) +{ + return x & (v2si){ 0xffff, 0 }; +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return x & (v8hi){ 0xffff, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return x & (v4hi){ 0xffff, 0, 0, 0 }; +} + +/* +** f_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return x & (v16qi){ 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return x & (v8qi){ 0xff, 0xff, 0, 0, 0, 0, 0, 0 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c new file mode 100644 index 0000000..0bddd96 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-be.c @@ -0,0 +1,77 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} + +/* +** f_v4si: +** fmov d0, d0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 6, 7, 2, 3 }); +} + +/* +** g_v4si: +** fmov d0, d0 +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 2, 3, 6, 7 }); +} + +/* +** h_v4si: +** fmov s0, s0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 4, 5, 6, 3 }); +} + +/* +** f_v4sf: +** fmov d0, d0 +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 6, 7, 2, 3 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c new file mode 100644 index 0000000..4545841 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c @@ -0,0 +1,129 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8-a") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef int v4si __attribute__ ((vector_size (16))); +typedef float v4sf __attribute__ ((vector_size (16))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov s0, s0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** g_v4hi: +** (?:(?!fmov).)* +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 3, 1, 4, 2 }); +} + +/* +** f_v8hi: +** fmov s0, s0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + +/* +** f_v4si: +** fmov d0, d0 +** ret +*/ +v4si +f_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 1, 4, 5 }); +} + +/* +** g_v4si: +** fmov d0, d0 +** ret +*/ +v4si +g_v4si (v4si x) +{ + return __builtin_shuffle ((v4si){ 0, 0, 0, 0 }, x, (v4si){ 4, 5, 2, 3 }); +} + +/* +** h_v4si: +** fmov s0, s0 +** ret +*/ +v4si +h_v4si (v4si x) +{ + return __builtin_shuffle (x, (v4si){ 0, 0, 0, 0 }, (v4si){ 0, 4, 5, 6 }); +} + +/* +** f_v4sf: +** fmov d0, d0 +** ret +*/ +v4sf +f_v4sf (v4sf x) +{ + return __builtin_shuffle (x, (v4sf){ 0, 0, 0, 0 }, (v4si){ 0, 1, 6, 7 }); +} + +/* +** f_v8qi: +** fmov s0, s0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 1, 2, 3, 10, 11, 12, 13 }); +} + +/* +** f_v16qi: +** fmov d0, d0 +** ret +*/ +v16qi +f_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 }); +} + +/* +** g_v16qi: +** fmov s0, s0 +** ret +*/ +v16qi +g_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 }); +} + diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c new file mode 100644 index 0000000..58212ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-4-be.c @@ -0,0 +1,54 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle ((v4hi){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return __builtin_shuffle ((v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c new file mode 100644 index 0000000..3449a51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-4-le.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef short v4hi __attribute__ ((vector_size (8))); +typedef char v8qi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); +typedef char v16qi __attribute__ ((vector_size (16))); + +/* +** f_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +f_v4hi (v4hi x) +{ + return __builtin_shuffle (x, (v4hi){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4hi: +** fmov h0, h0 +** ret +*/ +v4hi +g_v4hi (v4hi x) +{ + return __builtin_shuffle ((v4hi){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** f_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +f_v8hi (v8hi x) +{ + return __builtin_shuffle (x, (v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8hi: +** fmov h0, h0 +** ret +*/ +v8hi +g_v8hi (v8hi x) +{ + return __builtin_shuffle ((v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** f_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +f_v8qi (v8qi x) +{ + return __builtin_shuffle (x, (v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8qi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + + +/* +** g_v8qi: +** fmov h0, h0 +** ret +*/ +v8qi +g_v8qi (v8qi x) +{ + return __builtin_shuffle ((v8qi){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8qi){ 8, 9, 0, 1, 2, 3, 4, 5 }); +} + +/* +** h_v16qi: +** fmov h0, h0 +** ret +*/ +v16qi +h_v16qi (v16qi x) +{ + return __builtin_shuffle ( + x, (v16qi){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + (v16qi){ 0, 1, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c b/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c new file mode 100644 index 0000000..0fcefa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-5-be.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbig-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef __fp16 v4hf __attribute__ ((vector_size (8))); +typedef __fp16 v8hf __attribute__ ((vector_size (16))); +typedef __bf16 v4bf __attribute__ ((vector_size (8))); +typedef __bf16 v8bf __attribute__ ((vector_size (16))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +f_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +g_v4hf (v4hf x) +{ + return __builtin_shuffle ((v4hf){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** h_v4hf: +** fmov s0, s0 +** ret +*/ +v4hf +h_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +f_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +g_v8hf (v8hf x) +{ + return __builtin_shuffle ((v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} + +/* +** h_v8hf: +** fmov s0, s0 +** ret +*/ +v8hf +h_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} + +/* +** f_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +f_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 6, 3 }); +} + +/* +** g_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +g_v4bf (v4bf x) +{ + return __builtin_shuffle ((v4bf){ 0, 0, 0, 0 }, x, (v4hi){ 0, 1, 2, 7 }); +} + +/* +** h_v4bf: +** fmov s0, s0 +** ret +*/ +v4bf +h_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 4, 5, 2, 3 }); +} + +/* +** f_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +f_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 14, 7 }); +} + +/* +** g_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +g_v8bf (v8bf x) +{ + return __builtin_shuffle ((v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 0, 1, 2, 3, 4, 5, 6, 15 }); +} + +/* +** h_v8bf: +** fmov s0, s0 +** ret +*/ +v8bf +h_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 8, 9, 10, 11, 12, 13, 6, 7 }); +} diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c b/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c new file mode 100644 index 0000000..e3ad420 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmov-5-le.c @@ -0,0 +1,150 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlittle-endian" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#pragma GCC target ("arch=armv8.2-a+fp16") + +typedef __fp16 v4hf __attribute__ ((vector_size (8))); +typedef __fp16 v8hf __attribute__ ((vector_size (16))); +typedef __bf16 v4bf __attribute__ ((vector_size (8))); +typedef __bf16 v8bf __attribute__ ((vector_size (16))); +typedef short v4hi __attribute__ ((vector_size (8))); +typedef short v8hi __attribute__ ((vector_size (16))); + +/* +** f_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +f_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4hf: +** fmov h0, h0 +** ret +*/ +v4hf +g_v4hf (v4hf x) +{ + return __builtin_shuffle ((v4hf){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** h_v4hf: +** fmov s0, s0 +** ret +*/ +v4hf +h_v4hf (v4hf x) +{ + return __builtin_shuffle (x, (v4hf){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** f_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +f_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8hf: +** fmov h0, h0 +** ret +*/ +v8hf +g_v8hf (v8hf x) +{ + return __builtin_shuffle ((v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** h_v8hf: +** fmov s0, s0 +** ret +*/ +v8hf +h_v8hf (v8hf x) +{ + return __builtin_shuffle (x, (v8hf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} + +/* +** f_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +f_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 0, 4, 5, 6 }); +} + +/* +** g_v4bf: +** fmov h0, h0 +** ret +*/ +v4bf +g_v4bf (v4bf x) +{ + return __builtin_shuffle ((v4bf){ 0, 0, 0, 0 }, x, (v4hi){ 4, 0, 1, 2 }); +} + +/* +** h_v4bf: +** fmov s0, s0 +** ret +*/ +v4bf +h_v4bf (v4bf x) +{ + return __builtin_shuffle (x, (v4bf){ 0, 0, 0, 0 }, (v4hi){ 0, 1, 4, 5 }); +} + +/* +** f_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +f_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 8, 9, 10, 11, 12, 13, 14 }); +} + +/* +** g_v8bf: +** fmov h0, h0 +** ret +*/ +v8bf +g_v8bf (v8bf x) +{ + return __builtin_shuffle ((v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, x, + (v8hi){ 8, 0, 1, 2, 3, 4, 5, 6 }); +} + +/* +** h_v8bf: +** fmov s0, s0 +** ret +*/ +v8bf +h_v8bf (v8bf x) +{ + return __builtin_shuffle (x, (v8bf){ 0, 0, 0, 0, 0, 0, 0, 0 }, + (v8hi){ 0, 1, 8, 9, 10, 11, 12, 13 }); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c new file mode 100644 index 0000000..fae21b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120223.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=thead-c906" } */ +long foo(long x) { return x ^ 0x80000000; } + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 6de21a8..c6b25f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int16_t, +) +DEF_VX_BINARY_CASE_0(int16_t, +, add) +DEF_VX_BINARY_CASE_0(int16_t, -, sub) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index f46be7a..cb4ccfa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int32_t, +) +DEF_VX_BINARY_CASE_0(int32_t, +, add) +DEF_VX_BINARY_CASE_0(int32_t, -, sub) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 2b57b28..bf24984 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int64_t, +) +DEF_VX_BINARY_CASE_0(int64_t, +, add) +DEF_VX_BINARY_CASE_0(int64_t, -, sub) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index e139284..e830c75 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int8_t, +) +DEF_VX_BINARY_CASE_0(int8_t, +, add) +DEF_VX_BINARY_CASE_0(int8_t, -, sub) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c new file mode 100644 index 0000000..f08305e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +, add) +DEF_VX_BINARY_CASE_0(uint16_t, -, sub) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c new file mode 100644 index 0000000..1a7ae1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +, add) +DEF_VX_BINARY_CASE_0(uint32_t, -, sub) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c new file mode 100644 index 0000000..d478caf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +, add) +DEF_VX_BINARY_CASE_0(uint64_t, -, sub) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c new file mode 100644 index 0000000..aa3f5b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +, add) +DEF_VX_BINARY_CASE_0(uint8_t, -, sub) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index af3a40d..49e9957 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int32_t, +) +DEF_VX_BINARY_CASE_0(int16_t, +, add) +DEF_VX_BINARY_CASE_0(int16_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index 5f7c51c..869f9fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int64_t, +) +DEF_VX_BINARY_CASE_0(int32_t, +, add) +DEF_VX_BINARY_CASE_0(int32_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 420cf0e..6ba7143 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int8_t, +) +DEF_VX_BINARY_CASE_0(int64_t, +, add) +DEF_VX_BINARY_CASE_0(int64_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index b40d0b8..128a279 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int16_t, +) +DEF_VX_BINARY_CASE_0(int8_t, +, add) +DEF_VX_BINARY_CASE_0(int8_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c new file mode 100644 index 0000000..a2a35cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +, add) +DEF_VX_BINARY_CASE_0(uint16_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c new file mode 100644 index 0000000..bd89bfa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +, add) +DEF_VX_BINARY_CASE_0(uint32_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c new file mode 100644 index 0000000..134efe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +, add) +DEF_VX_BINARY_CASE_0(uint64_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c new file mode 100644 index 0000000..b1c7c5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +, add) +DEF_VX_BINARY_CASE_0(uint8_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index 1b47a59..aa21e10 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int32_t, +) +DEF_VX_BINARY_CASE_0(int16_t, +, add) +DEF_VX_BINARY_CASE_0(int16_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index 92ab1e8..7c37469 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int64_t, +) +DEF_VX_BINARY_CASE_0(int32_t, +, add) +DEF_VX_BINARY_CASE_0(int32_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 444707e..3efb0d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int8_t, +) +DEF_VX_BINARY_CASE_0(int64_t, +, add) +DEF_VX_BINARY_CASE_0(int64_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index f766907..d823ed9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_0(int16_t, +) +DEF_VX_BINARY_CASE_0(int8_t, +, add) +DEF_VX_BINARY_CASE_0(int8_t, -, sub) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c new file mode 100644 index 0000000..1ab09c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint16_t, +, add) +DEF_VX_BINARY_CASE_0(uint16_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c new file mode 100644 index 0000000..9247db7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint32_t, +, add) +DEF_VX_BINARY_CASE_0(uint32_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c new file mode 100644 index 0000000..139996b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint64_t, +, add) +DEF_VX_BINARY_CASE_0(uint64_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c new file mode 100644 index 0000000..d439dc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_0(uint8_t, +, add) +DEF_VX_BINARY_CASE_0(uint8_t, -, sub) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c new file mode 100644 index 0000000..0ae0566 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c index 8ad6098..86085d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c index 9a26601..9d89db3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c index 193e020..40b02db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c new file mode 100644 index 0000000..ca20106 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c new file mode 100644 index 0000000..6e2456c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c index 55b51fc..6e835d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c new file mode 100644 index 0000000..fc6aa47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index e5ec888..05742671 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c index 3d1ba7f..f990e34 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c index ed6c22d..3b189e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index d61f9df..3590b88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c index 2e9862b..994c7f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c new file mode 100644 index 0000000..2aceab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index ef44012..1414d85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c new file mode 100644 index 0000000..299f2da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c index 8094a2c..0e5ad32 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(int16_t, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(int16_t, -, sub, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c index 99f6614..b46b74a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int32_t, +, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(int32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(int32_t, -, sub, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c index 7ead9d0..13e64d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int8_t, +, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(int64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c index d80f0c0..1f58daa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int16_t, +, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(int8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(int8_t, -, sub, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c index 79b754b..2249cb2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -4,6 +4,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(uint16_t, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1(uint16_t, -, sub, VX_BINARY_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c index 2f70dcd..d768fc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint32_t, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1(uint32_t, -, sub, VX_BINARY_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c index ab06c51..b622640 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(int64_t, +, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(uint64_t, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1(uint64_t, -, sub, VX_BINARY_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c index 56d040b..6b3e6d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -3,6 +3,8 @@ #include "vx_binary.h" -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(uint8_t, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1(uint8_t, -, sub, VX_BINARY_BODY_X16) /* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index db802bd..f462109 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -3,16 +3,20 @@ #include <stdint.h> -#define DEF_VX_BINARY_CASE_0(T, OP) \ -void \ -test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \ -{ \ - for (unsigned i = 0; i < n; i++) \ - out[i] = in[i] OP x; \ +#define DEF_VX_BINARY_CASE_0(T, OP, NAME) \ +void \ +test_vx_binary_##NAME##_##T##_case_0 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP x; \ } -#define DEF_VX_BINARY_CASE_0_WRAP(T, OP) DEF_VX_BINARY_CASE_0(T, OP) -#define RUN_VX_BINARY_CASE_0(out, in, x, n) test_vx_binary_case_0(out, in, x, n) -#define RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) RUN_VX_BINARY_CASE_0(out, in, x, n) +#define DEF_VX_BINARY_CASE_0_WRAP(T, OP, NAME) \ + DEF_VX_BINARY_CASE_0(T, OP, NAME) +#define RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) \ + test_vx_binary_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) #define VX_BINARY_BODY(op) \ out[k + 0] = in[k + 0] op tmp; \ @@ -43,19 +47,21 @@ test_vx_binary_case_0 (T * restrict out, T * restrict in, T x, unsigned n) \ VX_BINARY_BODY_X64(op) \ VX_BINARY_BODY_X64(op) -#define DEF_VX_BINARY_CASE_1(T, OP, BODY) \ -void \ -test_vx_binary_case_1 (T * restrict out, T * restrict in, T x, unsigned n) \ -{ \ - unsigned k = 0; \ - T tmp = x + 3; \ - \ - while (k < n) \ - { \ - tmp = tmp ^ 0x3f; \ - BODY(OP) \ - } \ +#define DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) \ +void \ +test_vx_binary_##NAME##_##T##_case_1 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ } -#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, BODY) DEF_VX_BINARY_CASE_1(T, OP, BODY) +#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 11a32cb..7e68db9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6,7 +6,7 @@ #define TEST_BINARY_DATA(T, NAME) test_##T##_##NAME##_data #define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME) -int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = +int8_t TEST_BINARY_DATA(int8_t, add)[][3][N] = { { { 1 }, @@ -55,7 +55,7 @@ int8_t TEST_BINARY_DATA(int8_t, vadd)[][3][N] = }, }; -int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = +int16_t TEST_BINARY_DATA(int16_t, add)[][3][N] = { { { 1 }, @@ -104,7 +104,7 @@ int16_t TEST_BINARY_DATA(int16_t, vadd)[][3][N] = }, }; -int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = +int32_t TEST_BINARY_DATA(int32_t, add)[][3][N] = { { { 1 }, @@ -153,7 +153,7 @@ int32_t TEST_BINARY_DATA(int32_t, vadd)[][3][N] = }, }; -int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = +int64_t TEST_BINARY_DATA(int64_t, add)[][3][N] = { { { 1 }, @@ -202,7 +202,7 @@ int64_t TEST_BINARY_DATA(int64_t, vadd)[][3][N] = }, }; -uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = +uint8_t TEST_BINARY_DATA(uint8_t, add)[][3][N] = { { { 1 }, @@ -251,7 +251,7 @@ uint8_t TEST_BINARY_DATA(uint8_t, vadd)[][3][N] = }, }; -uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = +uint16_t TEST_BINARY_DATA(uint16_t, add)[][3][N] = { { { 1 }, @@ -300,7 +300,7 @@ uint16_t TEST_BINARY_DATA(uint16_t, vadd)[][3][N] = }, }; -uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = +uint32_t TEST_BINARY_DATA(uint32_t, add)[][3][N] = { { { 1 }, @@ -349,7 +349,7 @@ uint32_t TEST_BINARY_DATA(uint32_t, vadd)[][3][N] = }, }; -uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = +uint64_t TEST_BINARY_DATA(uint64_t, add)[][3][N] = { { { 1 }, @@ -398,4 +398,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, vadd)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + }, + { + { 253 }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + }, + { + { 65533 }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + { 4294967293 }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, + { + { 18446744073709551613ull }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h index bb35184..3c00dbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h @@ -13,7 +13,7 @@ main () T *in = TEST_DATA[i][1]; T *expect = TEST_DATA[i][2]; - TEST_RUN (out, in, x, N); + TEST_RUN (T, NAME, out, in, x, N); for (k = 0; k < N; k++) if (out[k] != expect[k]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c deleted file mode 100644 index 0266d44..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c deleted file mode 100644 index c541733..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c deleted file mode 100644 index e9e2162..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c deleted file mode 100644 index da71fff..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c deleted file mode 100644 index 7741d06..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c deleted file mode 100644 index 10ff20e..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c deleted file mode 100644 index fa5ab40..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c deleted file mode 100644 index 0374e1f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c deleted file mode 100644 index e3fc112..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint16_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c deleted file mode 100644 index f76971b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint32_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c deleted file mode 100644 index 09a4b42..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint64_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c deleted file mode 100644 index 5a0679f..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_0(uint8_t, +) - -/* { dg-final { scan-assembler-not {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c deleted file mode 100644 index a093fca..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint16_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c deleted file mode 100644 index 9f5843b..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint32_t, +, VX_BINARY_BODY_X4) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c deleted file mode 100644 index 0f00688..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c deleted file mode 100644 index 47707e8..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c deleted file mode 100644 index 72e6786..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint64_t, +, VX_BINARY_BODY) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c deleted file mode 100644 index e935be1..0000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ - -#include "vx_binary.h" - -DEF_VX_BINARY_CASE_1(uint8_t, +, VX_BINARY_BODY_X16) - -/* { dg-final { scan-assembler {vadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c index 306ad76..ac7bd2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int16_t +#define T int16_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c index 6ccdf7a..1e8b78f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int32_t +#define T int32_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c index 9484aa8..e2e352e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int64_t +#define T int64_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c index aeb330e..8a197e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T int8_t +#define T int8_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c index dafaa29..b616f39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint16_t +#define T uint16_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c index 6b285c8..bf0449c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint32_t +#define T uint32_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c index eeee4e1..2611892 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint64_t +#define T uint64_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c index 22d7a0e..60cfe7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c @@ -4,11 +4,12 @@ #include "vx_binary.h" #include "vx_binary_data.h" -#define T uint8_t +#define T uint8_t +#define NAME add -DEF_VX_BINARY_CASE_0_WRAP(T, +) +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) -#define TEST_DATA TEST_BINARY_DATA_WRAP(T, vadd) -#define TEST_RUN(out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(out, in, x, n) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) #include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c new file mode 100644 index 0000000..e28f954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c new file mode 100644 index 0000000..032ecad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c new file mode 100644 index 0000000..19bbe2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c new file mode 100644 index 0000000..7063a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c new file mode 100644 index 0000000..42a1508 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c new file mode 100644 index 0000000..2df5b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c new file mode 100644 index 0000000..c4f7e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c new file mode 100644 index 0000000..869380a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index 2225d30..6e97cae 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -13,6 +13,7 @@ sat_u_add_##T##_fmt_1 (T x, T y) \ { \ return (x + y) | (-(T)((T)(x + y) < x)); \ } +#define DEF_SAT_U_ADD_FMT_1_WRAP(T) DEF_SAT_U_ADD_FMT_1(T) #define DEF_SAT_U_ADD_FMT_2(T) \ T __attribute__((noinline)) \ @@ -20,6 +21,7 @@ sat_u_add_##T##_fmt_2 (T x, T y) \ { \ return (T)(x + y) >= x ? (x + y) : -1; \ } +#define DEF_SAT_U_ADD_FMT_2_WRAP(T) DEF_SAT_U_ADD_FMT_2(T) #define DEF_SAT_U_ADD_FMT_3(T) \ T __attribute__((noinline)) \ @@ -29,6 +31,7 @@ sat_u_add_##T##_fmt_3 (T x, T y) \ T overflow = __builtin_add_overflow (x, y, &ret); \ return (T)(-overflow) | ret; \ } +#define DEF_SAT_U_ADD_FMT_3_WRAP(T) DEF_SAT_U_ADD_FMT_3(T) #define DEF_SAT_U_ADD_FMT_4(T) \ T __attribute__((noinline)) \ @@ -37,6 +40,7 @@ sat_u_add_##T##_fmt_4 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } +#define DEF_SAT_U_ADD_FMT_4_WRAP(T) DEF_SAT_U_ADD_FMT_4(T) #define DEF_SAT_U_ADD_FMT_5(T) \ T __attribute__((noinline)) \ @@ -45,6 +49,7 @@ sat_u_add_##T##_fmt_5 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ } +#define DEF_SAT_U_ADD_FMT_5_WRAP(T) DEF_SAT_U_ADD_FMT_5(T) #define DEF_SAT_U_ADD_FMT_6(T) \ T __attribute__((noinline)) \ @@ -52,6 +57,7 @@ sat_u_add_##T##_fmt_6 (T x, T y) \ { \ return (T)(x + y) < x ? -1 : (x + y); \ } +#define DEF_SAT_U_ADD_FMT_6_WRAP(T) DEF_SAT_U_ADD_FMT_6(T) #define DEF_SAT_U_ADD_FMT_7(WT, T) \ T __attribute__((noinline)) \ @@ -64,11 +70,17 @@ sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ #define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) +#define RUN_SAT_U_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_1(T, x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) +#define RUN_SAT_U_ADD_FMT_2_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_2(T, x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) +#define RUN_SAT_U_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_3(T, x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) +#define RUN_SAT_U_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_4(T, x, y) #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) +#define RUN_SAT_U_ADD_FMT_5_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_5(T, x, y) #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y) +#define RUN_SAT_U_ADD_FMT_6_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_6(T, x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \ sat_u_add_uint16_t_##T##_fmt_7(x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h index 9f9f7d0..f100688 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h @@ -32,6 +32,11 @@ TEST_UNARY_STRUCT (uint16_t, uint32_t) TEST_UNARY_STRUCT (uint16_t, uint64_t) TEST_UNARY_STRUCT (uint32_t, uint64_t) +TEST_BINARY_STRUCT (uint8_t, usadd) +TEST_BINARY_STRUCT (uint16_t, usadd) +TEST_BINARY_STRUCT (uint32_t, usadd) +TEST_BINARY_STRUCT (uint64_t, usadd) + TEST_BINARY_STRUCT (int8_t, ssadd) TEST_BINARY_STRUCT (int16_t, ssadd) TEST_BINARY_STRUCT (int32_t, ssadd) @@ -236,6 +241,62 @@ TEST_UNARY_STRUCT_DECL(int32_t, int64_t) \ {-2147483648, -9223372036854775808ull}, }; +TEST_BINARY_STRUCT_DECL(uint8_t, usadd) TEST_BINARY_DATA(uint8_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +TEST_BINARY_STRUCT_DECL(uint16_t, usadd) TEST_BINARY_DATA(uint16_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +TEST_BINARY_STRUCT_DECL(uint32_t, usadd) TEST_BINARY_DATA(uint32_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +TEST_BINARY_STRUCT_DECL(uint64_t, usadd) TEST_BINARY_DATA(uint64_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + TEST_BINARY_STRUCT_DECL(int8_t, ssadd) TEST_BINARY_DATA(int8_t, ssadd)[] = { { 0, 0, 0}, diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c index cb3879d..fe015cc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c index c9a6080..8ee6501 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c index c19b7e2..d2c6af0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c index f197249..154edde 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c index 99b5c3a..1fc08bd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c index 13f5954..a52a230 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c index cdbea7b..d05ed33 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c index 508531c..fd39335 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c index bd935dc..7084272 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c index deccf9a..82de67d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c index 4f99367..d73f305 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c index 670932f..f572c44 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c index 33a595d..65c431f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c index 8a5b7c1..8a73fcd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c index fa20aae..0903e10 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c index 083d6e5..ffdd390 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c index a1d5d70..72ccd2f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c index 7608e71..34d1a4e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c index 496ab58..d502a58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c index 936028c..f611376 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c index d304288..5ef250d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c index 1a1ea59..ba95dbf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c index dc977d5..d0e9dfd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c index 8bc204e..b3d00df 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c @@ -2,24 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c index 25dc1d1..26c2778 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define WT uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP +#define T1 uint16_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c index 565b108..1f3e2f3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint16_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c index 6ff34fd..558f6ce 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint32_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c index 9e6e70a..ec5ac70 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP +#define T1 uint8_t +#define T2 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c index a1134ed..aa94eef 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP +#define T1 uint8_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c index ef9f7aa..6ac38ba 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c @@ -2,25 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define WT uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP +#define T1 uint8_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gfortran.dg/alloc_comp_auto_array_3.f90 b/gcc/testsuite/gfortran.dg/alloc_comp_auto_array_3.f90 index 2af089e..d0751f3 100644 --- a/gcc/testsuite/gfortran.dg/alloc_comp_auto_array_3.f90 +++ b/gcc/testsuite/gfortran.dg/alloc_comp_auto_array_3.f90 @@ -25,6 +25,6 @@ contains allocate (array(1)%bigarr) end function end -! { dg-final { scan-tree-dump-times "builtin_malloc" 3 "original" } } +! { dg-final { scan-tree-dump-times "builtin_malloc" 4 "original" } } ! { dg-final { scan-tree-dump-times "builtin_free" 3 "original" } } -! { dg-final { scan-tree-dump-times "while \\(1\\)" 4 "original" } } +! { dg-final { scan-tree-dump-times "while \\(1\\)" 5 "original" } } diff --git a/gcc/testsuite/gfortran.dg/alloc_comp_class_3.f03 b/gcc/testsuite/gfortran.dg/alloc_comp_class_3.f03 index 0753e33..8202d78 100644 --- a/gcc/testsuite/gfortran.dg/alloc_comp_class_3.f03 +++ b/gcc/testsuite/gfortran.dg/alloc_comp_class_3.f03 @@ -45,11 +45,10 @@ contains type(c), value :: d end subroutine - type(c) function c_init() ! { dg-warning "not set" } + type(c) function c_init() end function subroutine sub(d) type(u), value :: d end subroutine end program test_pr58586 - diff --git a/gcc/testsuite/gfortran.dg/alloc_comp_class_4.f03 b/gcc/testsuite/gfortran.dg/alloc_comp_class_4.f03 index 4a55d73..9ff38e3 100644 --- a/gcc/testsuite/gfortran.dg/alloc_comp_class_4.f03 +++ b/gcc/testsuite/gfortran.dg/alloc_comp_class_4.f03 @@ -51,14 +51,14 @@ contains type(t), value :: d end subroutine - type(c) function c_init() ! { dg-warning "not set" } + type(c) function c_init() end function class(c) function c_init2() ! { dg-warning "not set" } allocatable :: c_init2 end function - type(c) function d_init(this) ! { dg-warning "not set" } + type(c) function d_init(this) class(d) :: this end function @@ -102,4 +102,3 @@ program test_pr58586 call add_c(oe%init()) deallocate(oe) end program - diff --git a/gcc/testsuite/gfortran.dg/allocate_with_source_14.f03 b/gcc/testsuite/gfortran.dg/allocate_with_source_14.f03 index fd2db74..36c1245 100644 --- a/gcc/testsuite/gfortran.dg/allocate_with_source_14.f03 +++ b/gcc/testsuite/gfortran.dg/allocate_with_source_14.f03 @@ -210,5 +210,5 @@ program main call v%free() deallocate(av) end program -! { dg-final { scan-tree-dump-times "__builtin_malloc" 22 "original" } } +! { dg-final { scan-tree-dump-times "__builtin_malloc" 23 "original" } } ! { dg-final { scan-tree-dump-times "__builtin_free" 29 "original" } } diff --git a/gcc/testsuite/gfortran.dg/derived_constructor_comps_6.f90 b/gcc/testsuite/gfortran.dg/derived_constructor_comps_6.f90 index bdfa47b..406e031 100644 --- a/gcc/testsuite/gfortran.dg/derived_constructor_comps_6.f90 +++ b/gcc/testsuite/gfortran.dg/derived_constructor_comps_6.f90 @@ -129,5 +129,5 @@ contains prt_spec = name end function new_prt_spec3 end program main -! { dg-final { scan-tree-dump-times "__builtin_malloc" 15 "original" } } +! { dg-final { scan-tree-dump-times "__builtin_malloc" 16 "original" } } ! { dg-final { scan-tree-dump-times "__builtin_free" 33 "original" } } diff --git a/gcc/testsuite/gfortran.dg/derived_result_5.f90 b/gcc/testsuite/gfortran.dg/derived_result_5.f90 new file mode 100644 index 0000000..1ba4d19 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/derived_result_5.f90 @@ -0,0 +1,123 @@ +! { dg-do run } +! { dg-additional-options "-O2 -Wreturn-type" } +! +! PR fortran/85750 - default-initialization and functions returning derived type + +module bar + implicit none + type ilist + integer :: count = 42 + integer, pointer :: ptr(:) => null() + end type ilist + + type jlist + real, allocatable :: a(:) + integer :: count = 23 + end type jlist + +contains + + function make_list(i) + integer, intent(in) :: i + type(ilist), dimension(2) :: make_list + make_list(i)%count = i + end function make_list + + function make_list_res(i) result(list) + integer, intent(in) :: i + type(ilist), dimension(2) :: list + list(i)%count = i + end function make_list_res + + function make_jlist(i) + integer, intent(in) :: i + type(jlist), dimension(2) :: make_jlist + make_jlist(i)%count = i + end function make_jlist + + function make_jlist_res(i) result(list) + integer, intent(in) :: i + type(jlist), dimension(2) :: list + list(i)%count = i + end function make_jlist_res + + function empty_ilist() + type(ilist), dimension(2) :: empty_ilist + end function + + function empty_jlist() + type(jlist), dimension(2) :: empty_jlist + end function + + function empty_ilist_res() result (res) + type(ilist), dimension(2) :: res + end function + + function empty_jlist_res() result (res) + type(jlist), dimension(2) :: res + end function + +end module bar + +program foo + use bar + implicit none + type(ilist) :: mylist(2) = ilist(count=-2) + type(jlist), allocatable :: yourlist(:) + + mylist = ilist(count=-1) + if (any (mylist%count /= [-1,-1])) stop 1 + mylist = empty_ilist() + if (any (mylist%count /= [42,42])) stop 2 + mylist = ilist(count=-1) + mylist = empty_ilist_res() + if (any (mylist%count /= [42,42])) stop 3 + + allocate(yourlist(1:2)) + if (any (yourlist%count /= [23,23])) stop 4 + yourlist = jlist(count=-1) + if (any (yourlist%count /= [-1,-1])) stop 5 + yourlist = empty_jlist() + if (any (yourlist%count /= [23,23])) stop 6 + yourlist = jlist(count=-1) + yourlist = empty_jlist_res() + if (any (yourlist%count /= [23,23])) stop 7 + + mylist = make_list(1) + if (any (mylist%count /= [1,42])) stop 11 + mylist = make_list(2) + if (any (mylist%count /= [42,2])) stop 12 + mylist = (make_list(1)) + if (any (mylist%count /= [1,42])) stop 13 + mylist = [make_list(2)] + if (any (mylist%count /= [42,2])) stop 14 + + mylist = make_list_res(1) + if (any (mylist%count /= [1,42])) stop 21 + mylist = make_list_res(2) + if (any (mylist%count /= [42,2])) stop 22 + mylist = (make_list_res(1)) + if (any (mylist%count /= [1,42])) stop 23 + mylist = [make_list_res(2)] + if (any (mylist%count /= [42,2])) stop 24 + + yourlist = make_jlist(1) + if (any (yourlist%count /= [1,23])) stop 31 + yourlist = make_jlist(2) + if (any (yourlist%count /= [23,2])) stop 32 + yourlist = (make_jlist(1)) + if (any (yourlist%count /= [1,23])) stop 33 + yourlist = [make_jlist(2)] + if (any (yourlist%count /= [23,2])) stop 34 + + yourlist = make_jlist_res(1) + if (any (yourlist%count /= [1,23])) stop 41 + yourlist = make_jlist_res(2) + if (any (yourlist%count /= [23,2])) stop 42 + yourlist = (make_jlist_res(1)) + if (any (yourlist%count /= [1,23])) stop 43 + yourlist = [make_jlist_res(2)] + if (any (yourlist%count /= [23,2])) stop 44 + + deallocate (yourlist) +end program foo diff --git a/gcc/testsuite/lib/g++-dg.exp b/gcc/testsuite/lib/g++-dg.exp index 26bda65..042a917 100644 --- a/gcc/testsuite/lib/g++-dg.exp +++ b/gcc/testsuite/lib/g++-dg.exp @@ -27,6 +27,79 @@ proc g++-dg-prune { system text } { return [gcc-dg-prune $system $text] } +# Return a list of -std flags to use for TEST. +proc g++-std-flags { test } { + # If the testcase specifies a standard, use that one. + # If not, run it under several standards, allowing GNU extensions + # if there's a dg-options line. + if ![search_for $test "-std=*++"] { + if [search_for $test "dg-options"] { + set std_prefix "-std=gnu++" + } else { + set std_prefix "-std=c++" + } + + set low 0 + # Some directories expect certain minimums. + if { [string match "*/coroutines/*" $test] } { set low 20 } + if { [string match "*/modules/*" $test] } { set low 17 } + + # See g++.exp for the initial value of this list. + global gpp_std_list + if { [llength $gpp_std_list] > 0 } { + set std_list {} + foreach ver $gpp_std_list { + set cmpver $ver + if { $ver == 98 } { set cmpver 03 } + if { $ver ni $std_list + && $cmpver >= $low } { + lappend std_list $ver + } + } + } else { + # If the test mentions specific C++ versions, test those. + set lines [get_matching_lines $test {\{ dg* c++[0-9][0-9]}] + set std_list {} + foreach line $lines { + regexp {c\+\+([0-9][0-9])} $line -> ver + lappend std_list $ver + + if { $ver == 98 } { + # Leave low alone. + } elseif { [regexp {dg-do|dg-require-effective-target} $line] } { + set low $ver + } + } + #verbose "low: $low" 1 + + set std_list [lsort -unique $std_list] + + # If fewer than 3 specific versions are mentioned, add more. + # The order of this list is significant: first $cxx_default, + # then the oldest and newest, then others in rough order of + # importance based on test coverage and usage. + foreach ver { 17 98 26 11 20 14 23 } { + set cmpver $ver + if { $ver == 98 } { set cmpver 03 } + if { [llength $std_list] < 3 + && $ver ni $std_list + && $cmpver >= $low } { + lappend std_list $ver + } + } + verbose "std_list: $std_list" 1 + } + set option_list { } + foreach x $std_list { + if { $x eq "impcx" } then { set x "26 -fimplicit-constexpr" } + lappend option_list "${std_prefix}$x" + } + } else { + set option_list { "" } + } + return $option_list +} + # Modified dg-runtest that runs tests in multiple standard modes, # unless they specifically specify one standard. proc g++-dg-runtest { testcases flags default-extra-flags } { @@ -38,62 +111,7 @@ proc g++-dg-runtest { testcases flags default-extra-flags } { continue } - # If the testcase specifies a standard, use that one. - # If not, run it under several standards, allowing GNU extensions - # if there's a dg-options line. - if ![search_for $test "-std=*++"] { - if [search_for $test "dg-options"] { - set std_prefix "-std=gnu++" - } else { - set std_prefix "-std=c++" - } - - # See g++.exp for the initial value of this list. - global gpp_std_list - if { [llength $gpp_std_list] > 0 } { - set std_list $gpp_std_list - } else { - # If the test mentions specific C++ versions, test those. - set lines [get_matching_lines $test {\{ dg* c++[0-9][0-9]}] - set std_list {} - set low 0 - foreach line $lines { - regexp {c\+\+([0-9][0-9])} $line -> ver - lappend std_list $ver - - if { $ver == 98 } { - # Leave low alone. - } elseif { [regexp {dg-do|dg-require-effective-target} $line] } { - set low $ver - } - } - #verbose "low: $low" 1 - - set std_list [lsort -unique $std_list] - - # If fewer than 3 specific versions are mentioned, add more. - # The order of this list is significant: first $cxx_default, - # then the oldest and newest, then others in rough order of - # importance based on test coverage and usage. - foreach ver { 17 98 26 11 20 14 23 } { - set cmpver $ver - if { $ver == 98 } { set cmpver 03 } - if { [llength $std_list] < 3 - && $ver ni $std_list - && $cmpver > $low } { - lappend std_list $ver - } - } - verbose "std_list: $std_list" 1 - } - set option_list { } - foreach x $std_list { - if { $x eq "impcx" } then { set x "26 -fimplicit-constexpr" } - lappend option_list "${std_prefix}$x" - } - } else { - set option_list { "" } - } + set option_list [g++-std-flags $test] set nshort [file tail [file dirname $test]]/[file tail $test] |