diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
42 files changed, 986 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/pragma-target-1.c b/gcc/testsuite/gcc.target/riscv/pragma-target-1.c new file mode 100644 index 0000000..d1a0600 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pragma-target-1.c @@ -0,0 +1,59 @@ +/* Test for #pragma GCC target and push/pop options support in RISC-V */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ + +/* Default compilation options - no vector */ +void default_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector by default */ +#endif +} + +/* Change target to enable vector */ +#pragma GCC push_options +#pragma GCC target("arch=rv64gcv") +void vector_func(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector here */ +#endif +} +#pragma GCC pop_options + +/* Back to default - no vector */ +void after_pop_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector after pop */ +#endif +} + +/* Test multiple push/pop levels */ +#pragma GCC push_options +#pragma GCC target("arch=rv64gc") +void base_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector */ +#endif +} + +#pragma GCC push_options +#pragma GCC target("arch=rv64gcv") +void nested_vector_func(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector here */ +#endif +} +#pragma GCC pop_options + +void after_nested_pop_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector after nested pop */ +#endif +} +#pragma GCC pop_options + +/* Final function should be back to original default */ +void final_func(void) { +#ifdef __riscv_vector + __builtin_abort(); /* Should not have vector */ +#endif +} diff --git a/gcc/testsuite/gcc.target/riscv/pragma-target-2.c b/gcc/testsuite/gcc.target/riscv/pragma-target-2.c new file mode 100644 index 0000000..077bcdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pragma-target-2.c @@ -0,0 +1,26 @@ +/* Test for #pragma GCC target with tune parameter */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=rocket -O2" } */ + +void default_tune(void) { + /* Default tune is rocket */ +} + +#pragma GCC push_options +#pragma GCC target("tune=sifive-7-series") +void sifive_tune(void) { + /* Tune should be sifive-7-series */ +} +#pragma GCC pop_options + +void back_to_rocket(void) { + /* Tune should be back to rocket */ +} + +#pragma GCC target("arch=rv64gcv;tune=generic") +void combined_options(void) { +#ifndef __riscv_vector + __builtin_abort(); /* Should have vector */ +#endif + /* Tune should be generic */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c new file mode 100644 index 0000000..923c1f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +void __attribute__ (( target ("max-vectorization"))) +foo (char *restrict a, int *restrict b, short *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[d[i]]; + if (a[c[i]] != 0) + res = t * b[d[i]]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c new file mode 100644 index 0000000..fc5c2ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/max-vect-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mmax-vectorization -fdump-tree-vect-details" } */ + +void +foo (char *restrict a, int *restrict b, short *restrict c, + int *restrict d, int stride) +{ + if (stride <= 1) + return; + + for (int i = 0; i < 3; i++) + { + int res = c[i]; + int t = b[d[i]]; + if (a[c[i]] != 0) + res = t * b[d[i]]; + c[i] = res; + } +} + +/* { dg-final { scan-tree-dump "vectorized 1 loops in function" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c new file mode 100644 index 0000000..0beb3d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -mno-autovec-segment" } */ + +typedef struct { + int a[6]; + float b[3]; +} c; + +int d(c *e) { + int f =0; + for (; f < 3; f++) { + e->a[2 * f] = e->b[f]; + e->a[2 * f + 1] = -e->a[2 * f]; + e->a[2 * f] = f + 3 * e->a[2 * f]; + e->a[2 * f + 1] = f + 3 * e->a[2 * f + 1]; + } + return 0; +} + +/* { dg-final { scan-assembler-not "vsetivli.*zero,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c new file mode 100644 index 0000000..0de69b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr122635-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -mno-autovec-segment" } */ + +typedef struct { + int A[6]; + float b[]; +} a; + +int b(a *a) { + int b = 0; + for (; b < 3; b++) { + a->A[2 * b] = a->b[b] - b + a->A[2 * b]; + a->A[2 * b + 1] = b * a->A[2 * b + 1]; + } + return 0; +} + +/* { dg-final { scan-assembler-not "vsetivli.*zero,0" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c new file mode 100644 index 0000000..0562b56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d -mrvv-vector-bits=zvl -fsigned-char" } */ + +#include "pr123022.c" + +/* { dg-final { scan-assembler-not "vset.*zero,1," } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c new file mode 100644 index 0000000..1f5f165 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123022.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target rvv_zvl512b_ok } */ +/* { dg-options "-O3 -march=rv64gcv_zvl512b -mabi=lp64d -mrvv-vector-bits=zvl -fsigned-char" } */ +unsigned e[2][2]; +long a; +char c[2]; + +int +main () +{ + long long b; + c[1] = 3; + for (unsigned h = 0; h < 2; h++) + for (int i = c[0]; i < 5; i += 5) + for (int j = 0; j < 219; j++) + a = c[h] ? e[h][h] + 3326195747 : 0; + + b = a; + if (b != 3326195747) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c new file mode 100644 index 0000000..b3bf8da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +char p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c new file mode 100644 index 0000000..b8c4f22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +char p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c new file mode 100644 index 0000000..1a64b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +short p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c new file mode 100644 index 0000000..868f91b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-2.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +short p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c new file mode 100644 index 0000000..693a9118 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +int p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c new file mode 100644 index 0000000..d1a286b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +int p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c new file mode 100644 index 0000000..b55925e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4-run.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +long long p[128]; + +bool __attribute__((noipa)) +fand (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r |= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fand (n)) + __builtin_abort (); + + p[0] = 0; + for (int n = 1; n < 77; ++n) + if (fand (n)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fior (n)) + __builtin_abort (); + + p[0] = 1; + for (int n = 1; n < 77; ++n) + if (!fior (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c new file mode 100644 index 0000000..34a44b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-4.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +long long p[128]; + +bool __attribute__((noipa)) +fand () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r &= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fior () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r |= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c new file mode 100644 index 0000000..95570ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +char p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c new file mode 100644 index 0000000..f179970 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-5.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +char p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c new file mode 100644 index 0000000..267485b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +short p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c new file mode 100644 index 0000000..8486c6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-6.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +short p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c new file mode 100644 index 0000000..242147b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +int p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c new file mode 100644 index 0000000..cc14996 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-7.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +int p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c new file mode 100644 index 0000000..bf73da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ + +long long p[128]; + +bool __attribute__((noipa)) +fxort (int n) +{ + bool r = true; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf (int n) +{ + bool r = false; + for (int i = 0; i < n; ++i) + r ^= (p[i] != 0); + return r; +} + +int main() +{ + __builtin_memset (p, 1, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (fxort (n) != !(n & 1)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n) != (n & 1)) + __builtin_abort (); + + __builtin_memset (p, 0, sizeof(p)); + + for (int n = 0; n < 77; ++n) + if (!fxort (n)) + __builtin_abort (); + + for (int n = 0; n < 77; ++n) + if (fxorf (n)) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c new file mode 100644 index 0000000..6842f39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-bool-8.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -fdump-tree-vect-details" } */ + +long long p[128]; + +bool __attribute__((noipa)) +fxort () +{ + bool r = true; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +bool __attribute__((noipa)) +fxorf () +{ + bool r = false; + for (int i = 0; i < 16; ++i) + r ^= (p[i] != 0); + return r; +} + +/* { dg-final { scan-tree-dump-times "optimized: loop vectorized" 2 "vect" } } */ +/* { dg-final { scan-assembler-times {vcpop\.m\s+[atx][0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c index 14a961d..1b7a0d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c index 738caa8..8e2c631 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c index 1e7a977..a16623e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -32,3 +32,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c index 70257d3..be50b83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmslt.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c index bced156..fb50bae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c index cfb52fb..d79e0e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c index 31846ef..6cdaf5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c index ea28e2b..9e3879a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c index e3cddc4..e3ef3e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c index c5cce62..20039c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -28,4 +28,5 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c index 6ef8681..c973ea7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c index cc78959..e781c62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_SIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ +/* { dg-final { scan-assembler-not {vmslt.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index 764f301..a9bba40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -404,6 +404,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \ DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ + DEF_VX_BINARY_CASE_0_WRAP(T, <, lt) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index d4834c7..fad479a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6566,4 +6566,140 @@ uint64_t TEST_BINARY_DATA(uint64_t, ltu)[][3][N] = }, }; +int8_t TEST_BINARY_DATA(int8_t, lt)[][3][N] = +{ + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 127, 127, 127, 127, + -128, -128, -128, -128, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -128, -128, -128, -128, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, lt)[][3][N] = +{ + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -32768, -32768, -32768, -32768, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, lt)[][3][N] = +{ + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, lt)[][3][N] = +{ + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { -1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -2, -2, -2, -2, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c new file mode 100644 index 0000000..865a2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c new file mode 100644 index 0000000..eeb2a66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i32.c @@ -0,0 +1,16 @@ + +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c new file mode 100644 index 0000000..c3a2052 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c new file mode 100644 index 0000000..92a84f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmslt-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME lt + +DEF_VX_BINARY_CASE_0_WRAP(T, <, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" |