diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
23 files changed, 452 insertions, 5 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 3be4ade..9201883 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} /* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-1.c b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c new file mode 100644 index 0000000..5627e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-2.c b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c new file mode 100644 index 0000000..4c7d5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-3.c b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c new file mode 100644 index 0000000..7ff68f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-4.c b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c new file mode 100644 index 0000000..ef59b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-5.c b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c new file mode 100644 index 0000000..14e9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf_zcd -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-6.c b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c new file mode 100644 index 0000000..30cda55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-7.c b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c new file mode 100644 index 0000000..b06388b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-8.c b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c new file mode 100644 index 0000000..fa76050 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca_zcd -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c index e477414..fc86dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c index 7008eb5..4504158 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c index 89ebaaf..4ffc051 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c index cacbcaa..7ee8de2 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/bext-ext-2.c b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c new file mode 100644 index 0000000..aa170d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/bext-ext-2.c @@ -0,0 +1,74 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +struct obstack; +struct bitmap_head_def; +typedef struct bitmap_head_def *bitmap; +struct obstack +{ + long chunk_size; + struct _obstack_chunk *chunk; + char *object_base; + char *next_free; + char *chunk_limit; + long int temp; + int alignment_mask; + + + + struct _obstack_chunk *(*chunkfun) (void *, long); + void (*freefun) (void *, struct _obstack_chunk *); + void *extra_arg; + unsigned use_extra_arg:1; + unsigned maybe_empty_object:1; + + + + unsigned alloc_failed:1; + + +}; + +typedef unsigned long BITMAP_WORD; +typedef struct bitmap_obstack { + struct bitmap_element_def *elements; + struct bitmap_head_def *heads; + struct obstack obstack; +} bitmap_obstack; +typedef struct bitmap_element_def { + struct bitmap_element_def *next; + struct bitmap_element_def *prev; + unsigned int indx; + BITMAP_WORD bits[((128 + (8 + * 8 * 1u) - 1) / (8 + * 8 * 1u))]; +} bitmap_element; +bitmap_element *bitmap_find_bit (bitmap, unsigned int); + + +int +bitmap_bit_p (bitmap head, int bit) +{ + bitmap_element *ptr; + unsigned bit_num; + unsigned word_num; + + ptr = bitmap_find_bit (head, bit); + if (ptr == 0) + return 0; + + bit_num = bit % (8 + * 8 * 1u); + word_num = bit / (8 + * 8 * 1u) % ((128 + (8 + * 8 * 1u) - 1) / (8 + * 8 * 1u)); + + return (ptr->bits[word_num] >> bit_num) & 1; +} + +/* { dg-final { scan-assembler-times "bext\t" 1 } } */ +/* { dg-final { scan-assembler-not "slr\t"} } */ +/* { dg-final { scan-assembler-not "andi\t"} } */ + diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c new file mode 100644 index 0000000..cb28baf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ +/* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c new file mode 100644 index 0000000..1b1ee18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */ +/* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ +zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_sstc_svinval_svnapot_svpbmt_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined (__riscv__xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c new file mode 100644 index 0000000..1e27665 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ +/* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_ +xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_ +xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c new file mode 100644 index 0000000..6a54f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */ +/* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_ +zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_ +zbb_zbc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_ +xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c new file mode 100644 index 0000000..6bcd687 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */ +/* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfh) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvector)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c new file mode 100644 index 0000000..36a6267 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ +/* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei ) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfbfmin) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zca) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcd) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zvfbfmin) \ + && defined(__riscv_zvfbfwma) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sstc) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadsync) \ + && defined(__riscv_xtheadvdot)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/pr108016.c b/gcc/testsuite/gcc.target/riscv/pr108016.c new file mode 100644 index 0000000..b60df42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr108016.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +unsigned int addu (unsigned int a, unsigned int b) +{ + unsigned int out; + unsigned int overflow = __builtin_add_overflow (a, b, &out); + return overflow & out; +} + +int addi (int a, int b) +{ + int out; + int overflow = __builtin_add_overflow (a, b, &out); + return overflow & out; +} + +unsigned int subu (unsigned int a, unsigned int b) +{ + unsigned int out; + unsigned int overflow = __builtin_sub_overflow (a, b, &out); + return overflow & out; +} + +int subi (int a, int b) +{ + int out; + int overflow = __builtin_sub_overflow (a, b, &out); + return overflow & out; +} + +/* { dg-final { scan-assembler-not "sext\.w\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-1.c b/gcc/testsuite/gcc.target/riscv/pr118410-1.c new file mode 100644 index 0000000..4a8b847 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118410-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */ + +long orlow(long x) { return x | ((1L << 24) - 1); } + +/* { dg-final { scan-assembler-times "orn\t" 1 } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118410-2.c b/gcc/testsuite/gcc.target/riscv/pr118410-2.c new file mode 100644 index 0000000..b63a1d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118410-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64} } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32} } } */ + +long xorlow(long x) { return x ^ ((1L << 24) - 1); } + +/* { dg-final { scan-assembler-times "xnor\t" 1 } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ |