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-rw-r--r--gcc/config/i386/sse.md20
1 files changed, 16 insertions, 4 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c1ea04f..6b898dc 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1169,10 +1169,10 @@
;; Merge movsd/movhpd to movupd for TARGET_SSE_UNALIGNED_LOAD_OPTIMAL targets.
(define_peephole2
- [(set (match_operand:V2DF 0 "register_operand")
+ [(set (match_operand:V2DF 0 "sse_reg_operand")
(vec_concat:V2DF (match_operand:DF 1 "memory_operand")
(match_operand:DF 4 "const0_operand")))
- (set (match_operand:V2DF 2 "register_operand")
+ (set (match_operand:V2DF 2 "sse_reg_operand")
(vec_concat:V2DF (vec_select:DF (match_dup 2)
(parallel [(const_int 0)]))
(match_operand:DF 3 "memory_operand")))]
@@ -1181,13 +1181,25 @@
[(set (match_dup 2) (match_dup 4))]
"operands[4] = adjust_address (operands[1], V2DFmode, 0);")
+(define_peephole2
+ [(set (match_operand:DF 0 "sse_reg_operand")
+ (match_operand:DF 1 "memory_operand"))
+ (set (match_operand:V2DF 2 "sse_reg_operand")
+ (vec_concat:V2DF (match_operand:DF 4 "sse_reg_operand")
+ (match_operand:DF 3 "memory_operand")))]
+ "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
+ && REGNO (operands[4]) == REGNO (operands[2])
+ && ix86_operands_ok_for_move_multiple (operands, true, DFmode)"
+ [(set (match_dup 2) (match_dup 4))]
+ "operands[4] = adjust_address (operands[1], V2DFmode, 0);")
+
;; Merge movlpd/movhpd to movupd for TARGET_SSE_UNALIGNED_STORE_OPTIMAL targets.
(define_peephole2
[(set (match_operand:DF 0 "memory_operand")
- (vec_select:DF (match_operand:V2DF 1 "register_operand")
+ (vec_select:DF (match_operand:V2DF 1 "sse_reg_operand")
(parallel [(const_int 0)])))
(set (match_operand:DF 2 "memory_operand")
- (vec_select:DF (match_operand:V2DF 3 "register_operand")
+ (vec_select:DF (match_operand:V2DF 3 "sse_reg_operand")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL
&& ix86_operands_ok_for_move_multiple (operands, false, DFmode)"