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-rw-r--r--gcc/config/riscv/bitmanip.md36
-rw-r--r--gcc/config/riscv/iterators.md8
-rw-r--r--gcc/config/riscv/predicates.md10
-rw-r--r--gcc/config/riscv/riscv.md113
4 files changed, 62 insertions, 105 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a27fc3e..6f3d24a 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -351,6 +351,42 @@
"rolw\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+(define_insn_and_split "*<bitmanip_optab><GPR:mode>3_mask"
+ [(set (match_operand:GPR 0 "register_operand" "= r")
+ (bitmanip_rotate:GPR
+ (match_operand:GPR 1 "register_operand" " r")
+ (match_operator 4 "subreg_lowpart_operator"
+ [(and:GPR2
+ (match_operand:GPR2 2 "register_operand" "r")
+ (match_operand 3 "<GPR:shiftm1>" "<GPR:shiftm1p>"))])))]
+ "TARGET_ZBB || TARGET_ZBKB"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (bitmanip_rotate:GPR (match_dup 1)
+ (match_dup 2)))]
+ "operands[2] = gen_lowpart (QImode, operands[2]);"
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn_and_split "*<bitmanip_optab>si3_sext_mask"
+ [(set (match_operand:DI 0 "register_operand" "= r")
+ (sign_extend:DI (bitmanip_rotate:SI
+ (match_operand:SI 1 "register_operand" " r")
+ (match_operator 4 "subreg_lowpart_operator"
+ [(and:GPR
+ (match_operand:GPR 2 "register_operand" "r")
+ (match_operand 3 "const_si_mask_operand"))]))))]
+ "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:DI (bitmanip_rotate:SI (match_dup 1)
+ (match_dup 2))))]
+ "operands[2] = gen_lowpart (QImode, operands[2]);"
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "DI")])
+
;; orc.b (or-combine) is added as an unspec for the benefit of the support
;; for optimized string functions (such as strcmp).
(define_insn "orcb<mode>2"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 1d56324..8afe98e 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -117,7 +117,7 @@
(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
; bitmanip mode attribute
-(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+(define_mode_attr shiftm1 [(SI "const_si_mask_operand") (DI "const_di_mask_operand")])
(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
;; -------------------------------------------------------------------
@@ -174,6 +174,8 @@
(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
+(define_code_iterator bitmanip_rotate [rotate rotatert])
+
;; -------------------------------------------------------------------
;; Code Attributes
;; -------------------------------------------------------------------
@@ -271,7 +273,9 @@
(umax "umax")
(clz "clz")
(ctz "ctz")
- (popcount "popcount")])
+ (popcount "popcount")
+ (rotate "rotl")
+ (rotatert "rotr")])
(define_code_attr bitmanip_insn [(smin "min")
(smax "max")
(umin "minu")
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index e5adf06..ffcbb9a7 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -235,13 +235,15 @@
(and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))")))
-(define_predicate "const31_operand"
+(define_predicate "const_si_mask_operand"
(and (match_code "const_int")
- (match_test "INTVAL (op) == 31")))
+ (match_test "(INTVAL (op) & (GET_MODE_BITSIZE (SImode) - 1))
+ == GET_MODE_BITSIZE (SImode) - 1")))
-(define_predicate "const63_operand"
+(define_predicate "const_di_mask_operand"
(and (match_code "const_int")
- (match_test "INTVAL (op) == 63")))
+ (match_test "(INTVAL (op) & (GET_MODE_BITSIZE (DImode) - 1))
+ == GET_MODE_BITSIZE (DImode) - 1")))
(define_predicate "imm5_operand"
(and (match_code "const_int")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a917993..e773bc7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2048,45 +2048,6 @@
[(set_attr "type" "shift")
(set_attr "mode" "SI")])
-(define_insn_and_split "*<optab>si3_mask"
- [(set (match_operand:SI 0 "register_operand" "= r")
- (any_shift:SI
- (match_operand:SI 1 "register_operand" " r")
- (match_operator 4 "subreg_lowpart_operator"
- [(and:SI
- (match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "const_int_operand"))])))]
- "(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
- == GET_MODE_BITSIZE (SImode)-1"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_shift:SI (match_dup 1)
- (match_dup 2)))]
- "operands[2] = gen_lowpart (QImode, operands[2]);"
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*<optab>si3_mask_1"
- [(set (match_operand:SI 0 "register_operand" "= r")
- (any_shift:SI
- (match_operand:SI 1 "register_operand" " r")
- (match_operator 4 "subreg_lowpart_operator"
- [(and:DI
- (match_operand:DI 2 "register_operand" "r")
- (match_operand 3 "const_int_operand"))])))]
- "TARGET_64BIT
- && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
- == GET_MODE_BITSIZE (SImode)-1"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_shift:SI (match_dup 1)
- (match_dup 2)))]
- "operands[2] = gen_lowpart (QImode, operands[2]);"
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
(define_insn "<optab>di3"
[(set (match_operand:DI 0 "register_operand" "= r")
(any_shift:DI
@@ -2103,45 +2064,23 @@
[(set_attr "type" "shift")
(set_attr "mode" "DI")])
-(define_insn_and_split "*<optab>di3_mask"
- [(set (match_operand:DI 0 "register_operand" "= r")
- (any_shift:DI
- (match_operand:DI 1 "register_operand" " r")
+(define_insn_and_split "*<optab><GPR:mode>3_mask_1"
+ [(set (match_operand:GPR 0 "register_operand" "= r")
+ (any_shift:GPR
+ (match_operand:GPR 1 "register_operand" " r")
(match_operator 4 "subreg_lowpart_operator"
- [(and:SI
- (match_operand:SI 2 "register_operand" "r")
- (match_operand 3 "const_int_operand"))])))]
- "TARGET_64BIT
- && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
- == GET_MODE_BITSIZE (DImode)-1"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (any_shift:DI (match_dup 1)
- (match_dup 2)))]
- "operands[2] = gen_lowpart (QImode, operands[2]);"
- [(set_attr "type" "shift")
- (set_attr "mode" "DI")])
-
-(define_insn_and_split "*<optab>di3_mask_1"
- [(set (match_operand:DI 0 "register_operand" "= r")
- (any_shift:DI
- (match_operand:DI 1 "register_operand" " r")
- (match_operator 4 "subreg_lowpart_operator"
- [(and:DI
- (match_operand:DI 2 "register_operand" "r")
- (match_operand 3 "const_int_operand"))])))]
- "TARGET_64BIT
- && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
- == GET_MODE_BITSIZE (DImode)-1"
+ [(and:GPR2
+ (match_operand:GPR2 2 "register_operand" "r")
+ (match_operand 3 "<GPR:shiftm1>"))])))]
+ ""
"#"
"&& 1"
[(set (match_dup 0)
- (any_shift:DI (match_dup 1)
+ (any_shift:GPR (match_dup 1)
(match_dup 2)))]
"operands[2] = gen_lowpart (QImode, operands[2]);"
[(set_attr "type" "shift")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<GPR:MODE>")])
(define_insn "*<optab>si3_extend"
[(set (match_operand:DI 0 "register_operand" "= r")
@@ -2164,34 +2103,10 @@
(any_shift:SI
(match_operand:SI 1 "register_operand" " r")
(match_operator 4 "subreg_lowpart_operator"
- [(and:SI
- (match_operand:SI 2 "register_operand" " r")
- (match_operand 3 "const_int_operand"))]))))]
- "TARGET_64BIT
- && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
- == GET_MODE_BITSIZE (SImode)-1"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (sign_extend:DI
- (any_shift:SI (match_dup 1)
- (match_dup 2))))]
- "operands[2] = gen_lowpart (QImode, operands[2]);"
- [(set_attr "type" "shift")
- (set_attr "mode" "SI")])
-
-(define_insn_and_split "*<optab>si3_extend_mask_1"
- [(set (match_operand:DI 0 "register_operand" "= r")
- (sign_extend:DI
- (any_shift:SI
- (match_operand:SI 1 "register_operand" " r")
- (match_operator 4 "subreg_lowpart_operator"
- [(and:DI
- (match_operand:DI 2 "register_operand" " r")
- (match_operand 3 "const_int_operand"))]))))]
- "TARGET_64BIT
- && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
- == GET_MODE_BITSIZE (SImode)-1"
+ [(and:GPR
+ (match_operand:GPR 2 "register_operand" " r")
+ (match_operand 3 "const_si_mask_operand"))]))))]
+ "TARGET_64BIT"
"#"
"&& 1"
[(set (match_dup 0)
generated by cgit v1.1 at 2025-02-10 12:38:45 +0000