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-rw-r--r--gcc/config/i386/cpuid.h1
-rw-r--r--gcc/config/i386/i386-builtin.def6
-rw-r--r--gcc/config/i386/i386-c.cc2
-rw-r--r--gcc/config/i386/i386-isa.def1
-rw-r--r--gcc/config/i386/i386-options.cc4
-rw-r--r--gcc/config/i386/i386.opt5
-rw-r--r--gcc/config/i386/immintrin.h2
-rw-r--r--gcc/config/i386/sm4intrin.h70
-rw-r--r--gcc/config/i386/sse.md26
9 files changed, 116 insertions, 1 deletions
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index f9103f1..03fd6fc 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -134,6 +134,7 @@
/* %eax */
#define bit_SHA512 (1 << 0)
#define bit_SM3 (1 << 1)
+#define bit_SM4 (1 << 2)
#define bit_RAOINT (1 << 3)
#define bit_AVXVNNI (1 << 4)
#define bit_AVX512BF16 (1 << 5)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index b9e2bad..8738b3b 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -1660,6 +1660,12 @@ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_
BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
+/* SM4 */
+BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v4si, "__builtin_ia32_vsm4key4128", IX86_BUILTIN_VSM4KEY4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v8si, "__builtin_ia32_vsm4key4256", IX86_BUILTIN_VSM4KEY4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v4si, "__builtin_ia32_vsm4rnds4128", IX86_BUILTIN_VSM4RNDS4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v8si, "__builtin_ia32_vsm4rnds4256", IX86_BUILTIN_VSM4RNDS4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI)
+
/* SHA512 */
BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg1, "__builtin_ia32_vsha512msg1", IX86_BUILTIN_VSHA512MSG1, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI)
BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg2, "__builtin_ia32_vsha512msg2", IX86_BUILTIN_VSHA512MSG2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index c6311f1..0adec14 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -683,6 +683,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__SM3__");
if (isa_flag2 & OPTION_MASK_ISA2_SHA512)
def_or_undef (parse_in, "__SHA512__");
+ if (isa_flag2 & OPTION_MASK_ISA2_SM4)
+ def_or_undef (parse_in, "__SM4__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 28f2217..aeafcf8 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -120,3 +120,4 @@ DEF_PTA(AMX_COMPLEX)
DEF_PTA(AVXVNNIINT16)
DEF_PTA(SM3)
DEF_PTA(SHA512)
+DEF_PTA(SM4)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index d79ab01..347ed2d 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -242,7 +242,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX },
{ "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 },
{ "-msm3", OPTION_MASK_ISA2_SM3 },
- { "-msha512", OPTION_MASK_ISA2_SHA512 }
+ { "-msha512", OPTION_MASK_ISA2_SHA512 },
+ { "-msm4", OPTION_MASK_ISA2_SM4 }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1097,6 +1098,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16),
IX86_ATTR_ISA ("sm3", OPT_msm3),
IX86_ATTR_ISA ("sha512", OPT_msha512),
+ IX86_ATTR_ISA ("sm4", OPT_msm4),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index cf9dbca..db99568 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1298,3 +1298,8 @@ msha512
Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and
SHA512 built-in functions and code generation.
+
+msm4
+Target Mask(ISA2_SM4) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and
+SM4 built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 6f2bcef..ea14354 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -112,6 +112,8 @@
#include <sha512intrin.h>
+#include <sm4intrin.h>
+
#include <fmaintrin.h>
#include <f16cintrin.h>
diff --git a/gcc/config/i386/sm4intrin.h b/gcc/config/i386/sm4intrin.h
new file mode 100644
index 0000000..f58a782
--- /dev/null
+++ b/gcc/config/i386/sm4intrin.h
@@ -0,0 +1,70 @@
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <sm4intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _SM4INTRIN_H_INCLUDED
+#define _SM4INTRIN_H_INCLUDED
+
+#ifndef __SM4__
+#pragma GCC push_options
+#pragma GCC target("sm4")
+#define __DISABLE_SM4__
+#endif /* __SM4__ */
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_sm4key4_epi32 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A, (__v4si) __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sm4key4_epi32 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vsm4key4256 ((__v8si) __A, (__v8si) __B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_sm4rnds4_epi32 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_vsm4rnds4128 ((__v4si) __A, (__v4si) __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sm4rnds4_epi32 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vsm4rnds4256 ((__v8si) __A, (__v8si) __B);
+}
+
+#ifdef __DISABLE_SM4__
+#undef __DISABLE_SM4__
+#pragma GCC pop_options
+#endif /* __DISABLE_SM4__ */
+
+#endif /* _SM4INTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e16b2b5..7471932 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -223,6 +223,10 @@
UNSPEC_SHA512MSG2
UNSPEC_SHA512RNDS2
+ ;; For SM4 support
+ UNSPEC_SM4KEY4
+ UNSPEC_SM4RNDS4
+
])
(define_c_enum "unspecv" [
@@ -28680,6 +28684,28 @@
[(set_attr "type" "sselog1")
(set_attr "mode" "OI")])
+(define_insn "vsm4key4_<mode>"
+ [(set (match_operand:VI4_AVX 0 "register_operand" "=x")
+ (unspec:VI4_AVX
+ [(match_operand:VI4_AVX 1 "register_operand" "x")
+ (match_operand:VI4_AVX 2 "vector_operand" "xBm")]
+ UNSPEC_SM4KEY4))]
+ "TARGET_SM4"
+ "vsm4key4\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "other")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vsm4rnds4_<mode>"
+ [(set (match_operand:VI4_AVX 0 "register_operand" "=x")
+ (unspec:VI4_AVX
+ [(match_operand:VI4_AVX 1 "register_operand" "x")
+ (match_operand:VI4_AVX 2 "vector_operand" "xBm")]
+ UNSPEC_SM4RNDS4))]
+ "TARGET_SM4"
+ "vsm4rnds4\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "other")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn_and_split "avx512f_<castmode><avxsizesuffix>_<castmode>"
[(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m")
(vec_concat:AVX512MODE2P
generated by cgit v1.1 at 2025-09-02 20:06:48 +0000