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| author | Thiago Macieira <thiago.macieira@intel.com> | 2018-08-30 15:59:41 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-08-30 08:59:41 -0700 |
| commit | a73e818148ff2aa784a6691ec2d021ed07787e48 (patch) | |
| tree | af0016db3b0f6c5a9e73b142d8373fffc9bc9760 /libffi | |
| parent | 4e6a938029976924c3be5300e2d0caaae9d05c5d (diff) | |
| download | gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.zip gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.tar.gz gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.tar.bz2 | |
x86: Move AESNI generation to Skylake and Goldmont
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "Intel® AES New Instructions" "No".
[1] https://en.wikipedia.org/wiki/AES_instruction_set
2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.
From-SVN: r263989
Diffstat (limited to 'libffi')
0 files changed, 0 insertions, 0 deletions