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| author | Thiago Macieira <thiago.macieira@intel.com> | 2018-08-30 15:59:41 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-08-30 08:59:41 -0700 |
| commit | a73e818148ff2aa784a6691ec2d021ed07787e48 (patch) | |
| tree | af0016db3b0f6c5a9e73b142d8373fffc9bc9760 | |
| parent | 4e6a938029976924c3be5300e2d0caaae9d05c5d (diff) | |
| download | gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.zip gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.tar.gz gcc-a73e818148ff2aa784a6691ec2d021ed07787e48.tar.bz2 | |
x86: Move AESNI generation to Skylake and Goldmont
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "Intel® AES New Instructions" "No".
[1] https://en.wikipedia.org/wiki/AES_instruction_set
2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.
From-SVN: r263989
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 6 |
2 files changed, 9 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cce66bc..5d12003 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-08-30 Thiago Macieira <thiago.macieira@intel.com> + + * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES. + (PTA_SKYLAKE): Add PTA_AES. + (PTA_GOLDMONT): Likewise. + 2018-08-29 Jan Hubicka <jh@suse.cz> PR lto/86517 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c437c18..8672a66 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3479,7 +3479,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT; - const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL; + const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT; const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE @@ -3488,7 +3488,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED; - const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT + const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU @@ -3505,7 +3505,7 @@ ix86_option_override_internal (bool main_args_p, | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND; - const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE + const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT | PTA_FSGSBASE; const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID |