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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-12-18 17:49:08 +0800
committerPan Li <pan2.li@intel.com>2023-12-18 19:10:51 +0800
commit8c5d1d13882a0e58c308b95b1b51484721eafded (patch)
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RISC-V: Enable vect test for RV32
gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add RV32.
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