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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-12-18 17:49:08 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-12-18 19:10:51 +0800 |
| commit | 8c5d1d13882a0e58c308b95b1b51484721eafded (patch) | |
| tree | 5717e7471f2a602fdd167b4dc70443ff1d9ba2b3 | |
| parent | 000155e8eec27a35c9b431cbdc95f5d21d3e0872 (diff) | |
| download | gcc-8c5d1d13882a0e58c308b95b1b51484721eafded.zip gcc-8c5d1d13882a0e58c308b95b1b51484721eafded.tar.gz gcc-8c5d1d13882a0e58c308b95b1b51484721eafded.tar.bz2 | |
RISC-V: Enable vect test for RV32
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add RV32.
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index bd38d72..370df10 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11569,13 +11569,14 @@ proc check_vect_support_and_set_flags { } { } } elseif [istarget amdgcn-*-*] { set dg-do-what-default run - } elseif [istarget riscv64-*-*] { + } elseif [istarget riscv*-*-*] { if [check_effective_target_riscv_v] { lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi" set dg-do-what-default run } else { - lappend DEFAULT_VECTCFLAGS "-march=rv64gcv_zvfh" "-mabi=lp64d" - lappend DEFAULT_VECTCFLAGS "--param" "riscv-autovec-preference=scalable" + foreach item [add_options_for_riscv_v ""] { + lappend DEFAULT_VECTCFLAGS $item + } lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi" set dg-do-what-default compile } |