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| author | Falk Hueffner <falk@debian.org> | 2004-05-01 14:26:28 +0200 |
|---|---|---|
| committer | Falk Hueffner <falk@gcc.gnu.org> | 2004-05-01 14:26:28 +0200 |
| commit | ebade076e750e589043e25b83bb1d421143c2848 (patch) | |
| tree | 2119dd813dbb9bfae4d15e5f7ba881b226d9b7e3 /gcc | |
| parent | 0962c33d83e328593c8a76ee8a55de31e864b0d7 (diff) | |
| download | gcc-ebade076e750e589043e25b83bb1d421143c2848.zip gcc-ebade076e750e589043e25b83bb1d421143c2848.tar.gz gcc-ebade076e750e589043e25b83bb1d421143c2848.tar.bz2 | |
alpha.md (builtin_insbl, [...]): Disallow 0 as first input operand.
* config/alpha/alpha.md (builtin_insbl, builtin_inswl,
builtin_insll): Disallow 0 as first input operand.
From-SVN: r81387
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d442d30..2b79a6c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-05-01 Falk Hueffner <falk@debian.org> + * config/alpha/alpha.md (builtin_insbl, builtin_inswl, + builtin_insll): Disallow 0 as first input operand. + +2004-05-01 Falk Hueffner <falk@debian.org> + * config/alpha/alpha.c (alpha_rtx_costs): Fix shiftadd costs. 2004-05-01 Ulrich Weigand <uweigand@de.ibm.com> diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 64c88e3..3d3b731 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -7185,7 +7185,7 @@ (define_expand "builtin_insbl" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { @@ -7201,7 +7201,7 @@ (define_expand "builtin_inswl" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { @@ -7217,7 +7217,7 @@ (define_expand "builtin_insll" [(match_operand:DI 0 "register_operand" "") - (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_8bit_operand" "")] "" { |