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| author | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2024-11-10 12:30:02 +0100 |
|---|---|---|
| committer | Torbjörn SVENSSON <torbjorn.svensson@foss.st.com> | 2024-12-12 12:25:19 +0100 |
| commit | bdf75257aad299cbad5a62dd10a45139ac3aa369 (patch) | |
| tree | b0b55de77153c22f6a3ebb8f90dc6eaa43c2d45c /gcc | |
| parent | a2006457c676880315eee7728f2e0cf90bfbdd15 (diff) | |
| download | gcc-bdf75257aad299cbad5a62dd10a45139ac3aa369.zip gcc-bdf75257aad299cbad5a62dd10a45139ac3aa369.tar.gz gcc-bdf75257aad299cbad5a62dd10a45139ac3aa369.tar.bz2 | |
testsuite: arm: Use effective-target for its.c test [PR94531]
The test case gcc.target/arm/its.c was created together with restriction
of IT blocks for Cortex-M7. As the test case fails on all tunes that
does not match Cortex-M7, explicitly test it for Cortex-M7. To have some
additional faith that GCC does the correct thing, I also added another
variant of the test for Cortex-M3 that should allow longer IT blocks.
gcc/testsuite/ChangeLog:
PR testsuite/94531
* gcc.target/arm/its.c: Removed.
* gcc.target/arm/its-1.c: Copy of gcc.target/arm/its.c. Use
effective-target arm_cpu_cortex_m7.
* gcc.target/arm/its-2.c: Copy of gcc.target/arm/its.c. Use
effective-target arm_cpu_cortex_m3.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/its-1.c (renamed from gcc/testsuite/gcc.target/arm/its.c) | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/its-2.c | 24 |
2 files changed, 27 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/arm/its.c b/gcc/testsuite/gcc.target/arm/its-1.c index f81a0df..2730a2c 100644 --- a/gcc/testsuite/gcc.target/arm/its.c +++ b/gcc/testsuite/gcc.target/arm/its-1.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ -/* { dg-require-effective-target arm_cortex_m } */ -/* { dg-require-effective-target arm_thumb2 } */ +/* { dg-require-effective-target arm_cpu_cortex_m7_ok } */ /* { dg-options "-O2" } */ +/* { dg-add-options arm_cpu_cortex_m7 } */ + int test (int a, int b) { int r; diff --git a/gcc/testsuite/gcc.target/arm/its-2.c b/gcc/testsuite/gcc.target/arm/its-2.c new file mode 100644 index 0000000..2f4f629 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/its-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_cpu_cortex_m3_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_cpu_cortex_m3 } */ + +int test (int a, int b) +{ + int r; + if (a > 10) + { + r = a - b; + r += 10; + } + else + { + r = b - a; + r -= 7; + } + if (r > 0) + r -= 3; + return r; +} +/* Ensure there is an IT block with at least 2 instructions. */ +/* { dg-final { scan-assembler "\\sit\[te\]{2}" } } */ |