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| author | Matthew Wahab <matthew.wahab@arm.com> | 2015-06-29 16:03:34 +0000 |
|---|---|---|
| committer | Matthew Wahab <mwahab@gcc.gnu.org> | 2015-06-29 16:03:34 +0000 |
| commit | 6b3a1ce9f4f8b780f5fab81cddb81f517a036532 (patch) | |
| tree | ac3155f5959d9c673ae9a1110de94891d966c151 /gcc | |
| parent | e85f8bb8b3aecde1a86c40ffc3a8ab28bc80276c (diff) | |
| download | gcc-6b3a1ce9f4f8b780f5fab81cddb81f517a036532.zip gcc-6b3a1ce9f4f8b780f5fab81cddb81f517a036532.tar.gz gcc-6b3a1ce9f4f8b780f5fab81cddb81f517a036532.tar.bz2 | |
re PR target/65697 (__atomic memory barriers not strong enough for __sync builtins)
2015-06-29 Matthew Wahab <matthew.wahab@arm.com>
PR target/65697
* config/armc/arm.c (arm_split_atomic_op): For ARMv8, replace an
initial acquire barrier with final barrier.
From-SVN: r225132
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 10 |
2 files changed, 15 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b079301..2a7ef9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-06-29 Matthew Wahab <matthew.wahab@arm.com> + + PR target/65697 + * config/armc/arm.c (arm_split_atomic_op): For ARMv8, replace an + initial acquire barrier with final barrier. + 2015-06-29 Richard Henderson <rth@redhat.com> * config/i386/constraints.md (Bf): New constraint. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9f30041..5667763 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27679,6 +27679,8 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, rtx_code_label *label; rtx x; + bool is_armv8_sync = arm_arch8 && is_mm_sync (model); + bool use_acquire = TARGET_HAVE_LDACQ && !(is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)); @@ -27687,6 +27689,11 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, && !(is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model)); + /* For ARMv8, a load-acquire is too weak for __sync memory orders. Instead, + a full barrier is emitted after the store-release. */ + if (is_armv8_sync) + use_acquire = false; + /* Checks whether a barrier is needed and emits one accordingly. */ if (!(use_acquire || use_release)) arm_pre_atomic_barrier (model); @@ -27757,7 +27764,8 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, emit_unlikely_jump (gen_cbranchsi4 (x, cond, const0_rtx, label)); /* Checks whether a barrier is needed and emits one accordingly. */ - if (!(use_acquire || use_release)) + if (is_armv8_sync + || !(use_acquire || use_release)) arm_post_atomic_barrier (model); } |