RISC-V: Refactor the test files for all other vector SAT ALU

This patch would like to refactor the all the other testcases of vector
SAT ALU after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.
* Reconcile the dump check based on option no-opts and/or any-opts.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Refine
	the include file, remove unnecessary options and reconcile the
	dump check based on options.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Removed.

Signed-off-by: Pan Li <pan2.li@intel.com>

131 files changed, 574 insertions, 1145 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
index 12d8c01..38d1057 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
index 338e415..b1d0ad0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
index 83ccd4b..a7cb22d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
index 06b4104..28c2429 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
index dec0359..19c7677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
index 72b2d67..572a4bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
index 3ca4458..f41e939 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
index e3a7bfc..af21bf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
index c10dc09..88304e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
index d1352ed..f5a312e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
index b86887d..3275721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
index 79ce8dc..8b3953f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
index 4497f0c..7057c6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
index 9f06e6a..f9c968d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
index e806fd0..cd96056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
index 254bb18..24dfbe9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
index 7dc8e10..f21061f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
index b304cd6..635341e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
index 228c5a8..bfdf829 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
index af40837..6ea5ae8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-1-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
index 89cd450..2286e6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
index aa91300..051bf7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
index 0610703..12879ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
index 3b2a24d..9c5b0a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-2-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
index 9e26214..95fac36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
index ed6bc57..a35ffb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
index d62a4a7..d112f27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
index 56b0f22..ee3c12c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-3-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
index 974fd40..e12d7d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
index 375a59b..dd17f18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
index 2a301ec..065245c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
index 51dd327..a009307 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-run-4-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T  int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
index dd87dfd..51a3b1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
index caf646f..95a11e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
index f06267a..1f40a2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
index f784937..4a5bdfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
index 1e5289c..034bff3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
index 2fb604b..f437c54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
index 3e26e78..1a0e2d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
index 6379770..88bc1f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
index aa996f3..d56dd05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
index 2a15556..db23955 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
index d9649fc..f9c30fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
index 1ad2b3f..a1b21ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
index 392366d..9330437 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
index 2b16049..c17b25f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
index b444d2e..1adc420 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
index 0660658..b215b4db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
index 72ec727..13e68df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
index 7915d54..7bd2303 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
index 2ac96aa..9b85ac5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
index 7fe8f27..912e2b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
index 9650056..f831f79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
index b1ed04f..f67afcd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
index 94afc44..d0bf273 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
index 483c9e8..d7ea858 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
index 49c076a..c62175e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
index a2a1aa4..0e5fe79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
index ba09734..90f1a3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
index 7bc191d..69f397a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
index b896cbe..53a8f86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
index 67477e5..af49f56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
index c970573..f2790d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
index 629c073..c68eaf7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
index c70c832..7f81ee1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
index d1967ba..f7da852 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
index 8e2625f..b3d3d07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
index b75a82e..c16337c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
index a6eb2d5..171efe7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
index fd01c74..9d0e1fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
index 6af6153..8175a70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
index aee896e..2f6a1ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
index ce3ca80..3862e85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
index b3cb744..dcde698 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
index 64f140f..4fc64a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
index 9bd95a5..c80621a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
index 0cb9d77..a60ff87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
index 8d766e3..1257dc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
index 98ede14..9a1fe30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
index 2d9870f..7d6a8e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
@@ -1,9 +1,14 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+     "-O3"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+     "-O2"
+   } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
index 508cf34..c04a4ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
index 3b7c3b6..a4eb523 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
index 508cf34..c04a4ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
index 4a049ce..814ca89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
index 15b6670..8540ca0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
index 5a1dd85..d15ba0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-1-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
index a98447d..0be8714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
index 93f40b6..2691d11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
index a98447d..0be8714 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
index c946ac3..b9d0483 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
index 1d3b034..97fd9ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
index 98a637e..1798ef6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-2-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
index 0b658f3..bf84ce0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
index 41e1789..cbaeb83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
index 0b658f3..bf84ce0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
index 28cd5c8..7004c36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
index a6501f9..43cff84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
index eef36e8..e145561 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-3-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
index d07b736..e3f3584 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
index 06afa3f..5e36e39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
index d07b736..e3f3584 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
index de26b5c..cbfac22 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
index c1907f7..e5fad52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
index 645d764..480ff99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-4-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
index c2b7b7b..b924cc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
index 238e0d7..1751bcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
index c2b7b7b..b924cc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
index e5ef086..3d9ddd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
index 61158ef..84dc728 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
index b688c11..1a0133d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-5-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
index 457abd6..7c7f404 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
index 694a771..34a07b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
index 457abd6..7c7f404 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
index 6fb64a3..bb8058d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
index 0c8bc74..a9929c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
index 3c4513c..87634e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-6-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
index 53c0464..2f1e111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
index 132de83..55ca0cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
index 53c0464..2f1e111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
index 3747149..09e08ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
index 8a85d40..98dc64d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
index 11f758f..2a15746 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-7-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
index 4964599..e36aeed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i16-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
index 6c424b2..158f00e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
index 4964599..e36aeed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i32-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
index e7b6cdb..57d9b47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
index 02456e9..730ef4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
index 23cc7f0..56fa74bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-run-8-i64-to-i8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 int8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
index 63d2391..972629a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip-run.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
index 16ff0c6..51f1ee5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c
@@ -1,10 +1,20 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
-/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
-/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 6 "expand" { target { any-opts
+     "-mrvv-vector-bits=scalable"
+   } } } } */
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+     "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 3 { target { any-ops
+     "-mrvv-vector-bits=scalable"
+   } } } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 2 { target { any-ops
+     "-mrvv-vector-bits=zvl"
+   } } } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
deleted file mode 100644
index cb419553..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ /dev/null
@@ -1,886 +0,0 @@
-#ifndef HAVE_VEC_SAT_ARITH
-#define HAVE_VEC_SAT_ARITH
-
-#include <stdint-gcc.h>
-#include <stdbool.h>
-
-#define VALIDATE_RESULT(out, expect, N)              \
-  do                                                 \
-    {                                                \
-      for (unsigned i = 0; i < N; i++)               \
-        if (out[i] != expect[i]) __builtin_abort (); \
-    }                                                \
-  while (false)
-
-/******************************************************************************/
-/* Saturation Add (unsigned and signed)                                       */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_ADD_FMT_1(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x + y) | (-(T)((T)(x + y) < x));                     \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_2(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (T)(x + y) >= x ? (x + y) : -1;                       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_3(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_add_overflow (x, y, &ret);              \
-      out[i] = (T)(-overflow) | ret;                                 \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_4(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_5(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_6(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x <= (T)(x + y) ? (x + y) : -1;                       \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_7(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (T)(x + y) < x ? -1 : (x + y);                        \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_ADD_FMT_8(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x > (T)(x + y) ? -1 : (x + y);                        \
-    }                                                                \
-}
-
-#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
-  vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1;         \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM);          \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)                          \
-T __attribute__((noinline))                                          \
-vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  T ret;                                                             \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
-    }                                                                \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)
-
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)                               \
-T __attribute__((noinline))                                               \
-vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit)      \
-{                                                                         \
-  unsigned i;                                                             \
-  T ret;                                                                  \
-  for (i = 0; i < limit; i++)                                             \
-    {                                                                     \
-      out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \
-    }                                                                     \
-}
-#define DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_3(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N)
-
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_add_imm##IMM##_##T##_fmt_4(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N)
-
-#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum = (UT)x + (UT)y;                                         \
-      out[i] = (x ^ y) < 0                                           \
-        ? sum                                                        \
-        : (sum ^ x) >= 0                                             \
-          ? sum                                                      \
-          : x < 0 ? MIN : MAX;                                       \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_1_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum = (UT)x + (UT)y;                                         \
-      if ((x ^ y) < 0 || (sum ^ x) >= 0)                             \
-        out[i] = sum;                                                \
-      else                                                           \
-        out[i] = x < 0 ? MIN : MAX;                                  \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_2_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum;                                                         \
-      bool overflow = __builtin_add_overflow (x, y, &sum);           \
-      out[i] = overflow ? x < 0 ? MIN : MAX : sum;                   \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T sum;                                                         \
-      bool overflow = __builtin_add_overflow (x, y, &sum);           \
-      out[i] = !overflow ? sum : x < 0 ? MIN : MAX;                  \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
-
-#define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_2(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_3(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_s_add_##T##_fmt_4(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N)
-
-/******************************************************************************/
-/* Saturation Sub (Unsigned and Signed)                                       */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_SUB_FMT_1(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x - y) & (-(T)(x >= y));                             \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_2(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = (x - y) & (-(T)(x > y));                              \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_3(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x > y ? x - y : 0;                                    \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_4(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x >= y ? x - y : 0;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_5(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x < y ? 0 : x - y;                                    \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_6(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      out[i] = x <= y ? 0 : x - y;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_7(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_sub_overflow (x, y, &ret);              \
-      out[i] = ret & (T)(overflow - 1);                              \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_8(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      T overflow = __builtin_sub_overflow (x, y, &ret);              \
-      out[i] = ret & (T)-(!overflow);                                \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_9(T)                                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T ret;                                                         \
-      bool overflow = __builtin_sub_overflow (x, y, &ret);           \
-      out[i] = overflow ? 0 : ret;                                   \
-    }                                                                \
-}
-
-#define DEF_VEC_SAT_U_SUB_FMT_10(T)                                   \
-void __attribute__((noinline))                                        \
-vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      T x = op_1[i];                                                  \
-      T y = op_2[i];                                                  \
-      T ret;                                                          \
-      bool overflow = __builtin_sub_overflow (x, y, &ret);            \
-      out[i] = !overflow ? ret : 0;                                   \
-    }                                                                 \
-}
-
-#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2)                             \
-void __attribute__((noinline))                                    \
-vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
-{                                                                 \
-  T2 a;                                                           \
-  T1 *p = x;                                                      \
-  do {                                                            \
-    a = *--p;                                                     \
-    *p = (T1)(a >= b ? a - b : 0);                                \
-  } while (--limit);                                              \
-}
-#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
-
-#define DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) \
-void __attribute__((noinline))             \
-vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit)  \
-{                                                   \
-  unsigned i;                                       \
-  for (i = 0; i < limit; i++)                       \
-    out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0;  \
-}
-
-#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \
-  DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM)
-
-#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
-  vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N);             \
-  VALIDATE_RESULT (out, expect, N)
-#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
-  RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N)
-
-#define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus = (UT)x - (UT)y;                                       \
-      out[i] = (x ^ y) >= 0                                          \
-        ? minus                                                      \
-        : (minus ^ x) >= 0                                           \
-          ? minus                                                    \
-          : x < 0 ? MIN : MAX;                                       \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_1_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus = (UT)x - (UT)y;                                       \
-      out[i] = (x ^ y) >= 0 || (minus ^ x) >= 0                      \
-        ? minus : x < 0 ? MIN : MAX;                                 \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_2_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_2(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus;                                                       \
-      bool overflow = __builtin_sub_overflow (x, y, &minus);         \
-      out[i] = overflow ? x < 0 ? MIN : MAX : minus;                 \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_3_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)
-
-#define DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)                     \
-void __attribute__((noinline))                                       \
-vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      T x = op_1[i];                                                 \
-      T y = op_2[i];                                                 \
-      T minus;                                                       \
-      bool overflow = __builtin_sub_overflow (x, y, &minus);         \
-      out[i] = !overflow ? minus : x < 0 ? MIN : MAX;                \
-    }                                                                \
-}
-#define DEF_VEC_SAT_S_SUB_FMT_4_WRAP(T, UT, MIN, MAX) \
-  DEF_VEC_SAT_S_SUB_FMT_4(T, UT, MIN, MAX)
-
-#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
-  vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
-  vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N)
-#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \
-  RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \
-
-#define RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_1(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_1(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_2(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_2(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_3(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_3(T, out, op_1, op_2, N)
-
-#define RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N) \
-  vec_sat_s_sub_##T##_fmt_4(out, op_1, op_2, N)
-#define RUN_VEC_SAT_S_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) \
-  RUN_VEC_SAT_S_SUB_FMT_4(T, out, op_1, op_2, N)
-
-/******************************************************************************/
-/* Saturation Sub Truncated (Unsigned and Signed)                             */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)                   \
-void __attribute__((noinline))                                       \
-vec_sat_u_sub_trunc_##OUT_T##_fmt_1 (OUT_T *out, IN_T *op_1, IN_T y, \
-				     unsigned limit)                 \
-{                                                                    \
-  unsigned i;                                                        \
-  for (i = 0; i < limit; i++)                                        \
-    {                                                                \
-      IN_T x = op_1[i];                                              \
-      out[i] = (OUT_T)(x >= y ? x - y : 0);                          \
-    }                                                                \
-}
-
-#define RUN_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T, out, op_1, y, N) \
-  vec_sat_u_sub_trunc_##OUT_T##_fmt_1(out, op_1, y, N)
-
-/******************************************************************************/
-/* Saturation Truncation (Unsigned and Signed)                                */
-/******************************************************************************/
-#define DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      bool overflow = x > (WT)(NT)(-1);                               \
-      out[i] = ((NT)x) | (NT)-overflow;                               \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_1(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT max = (WT)(NT)-1;                                            \
-      out[i] = in[i] > max ? (NT)max : (NT)in[i];                     \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_2(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT max = (WT)(NT)-1;                                            \
-      out[i] = in[i] <= max ? (NT)in[i] : (NT)max;                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_3(NT, WT)
-
-#define DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)                             \
-void __attribute__((noinline))                                        \
-vec_sat_u_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      bool not_overflow = in[i] <= (WT)(NT)(-1);                      \
-      out[i] = ((NT)in[i]) | (NT)((NT)not_overflow - 1);              \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_VEC_SAT_U_TRUNC_FMT_4(NT, WT)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_1 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN <= x && x <= (WT)NT_MAX                     \
-	? trunc                                                       \
-	: x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_1(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_2 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN < x && x < (WT)NT_MAX                       \
-	? trunc                                                       \
-	: x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_3 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN < x && x <= (WT)NT_MAX                      \
-	? trunc                                                       \
-	: x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_4 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN <= x && x < (WT)NT_MAX                      \
-	? trunc                                                       \
-	: x < 0 ? NT_MIN : NT_MAX;                                    \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_4(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_5 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN > x || x > (WT)NT_MAX                       \
-	? x < 0 ? NT_MIN : NT_MAX                                     \
-	: trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_6 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN >= x || x > (WT)NT_MAX                      \
-	? x < 0 ? NT_MIN : NT_MAX                                     \
-	: trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_7 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN > x || x >= (WT)NT_MAX                      \
-	? x < 0 ? NT_MIN : NT_MAX                                     \
-	: trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN, NT_MAX)
-
-#define DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX)             \
-void __attribute__((noinline))                                        \
-vec_sat_s_trunc_##NT##_##WT##_fmt_8 (NT *out, WT *in, unsigned limit) \
-{                                                                     \
-  unsigned i;                                                         \
-  for (i = 0; i < limit; i++)                                         \
-    {                                                                 \
-      WT x = in[i];                                                   \
-      NT trunc = (NT)x;                                               \
-      out[i] = (WT)NT_MIN >= x || x >= (WT)NT_MAX                     \
-	? x < 0 ? NT_MIN : NT_MAX                                     \
-	: trunc;                                                      \
-    }                                                                 \
-}
-#define DEF_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, NT_MIN, NT_MAX) \
-  DEF_VEC_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN, NT_MAX)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_1 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_1(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_2 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_2(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_3 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_3(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N) \
-  vec_sat_u_trunc_##NT##_##WT##_fmt_4 (out, in, N)
-#define RUN_VEC_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_U_TRUNC_FMT_4(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_1 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_1_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_1(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_2 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_2_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_2(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_3 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_3_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_3(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_4 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_4_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_4(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_5 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_5_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_5(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_6 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_6_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_6(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_7 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_7_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_7(NT, WT, out, in, N)
-
-#define RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N) \
-  vec_sat_s_trunc_##NT##_##WT##_fmt_8 (out, in, N)
-#define RUN_VEC_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, out, in, N) \
-  RUN_VEC_SAT_S_TRUNC_FMT_8(NT, WT, out, in, N)
-
-#endif